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7.2.2
DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
7
Bit Name
CHNE
Initial Value
Undefined
R/W
Initial
Bit
Bit Name
Value
Undefined
7
CHNE
Undefined
6
CHNS
Undefined
5
DISEL
Undefined
4
DTS
6
5
CHNS
DISEL
Undefined
Undefined
R/W
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see 7.5.7, Chain
Transfer. The chain transfer condition is selected by the
CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Section 7 Data Transfer Controller (DTC)
4
3
DTS
DM1
Undefined
Undefined
Rev.2.00 Jun. 28, 2007 Page 221 of 666
2
1
DM0
Undefined
Undefined
REJ09B0311-0200
0
Undefined
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