Section 7 Data Transfer Controller; Overview; Features - Renesas H8S/2319 series Hardware Manual

Section 7 Data Transfer Controller

7.1

Overview

The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by
an interrupt or software.
7.1.1

Features

The features of the DTC are:
• Transfer possible over any number of channels
 Transfer information is stored in memory
 One activation source can trigger a number of data transfers (chain transfer)
 Chain transfer execution can be set after data transfer (when counter = 0)
• Selection of transfer modes
 Normal, repeat, and block transfer modes available
 Incrementing, decrementing, and fixing of source and destination addresses can be selected
• Direct specification of 16-Mbyte address space possible
 24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
 An interrupt request can be issued to the CPU after one data transfer ends
 An interrupt request can be issued to the CPU after all the specified data transfers have
ended
• Activation by software is possible
• Module stop mode can be set
 The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode
Rev. 5.00, 12/03, page 183 of 1088