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4.11 Data Transfer Controller (DTC)
The DTC operates during emulation execution and in the break mode. When a transfer request occurs,
the emulator carries out DTC transfer. The DTC RAM data is not accessable during run mode i.e., no
POTF is possible for DTC RAM.
NOTE: The DTC is connected to the area from adress H'FF-EBC0 to H'FF-EFBF in the internal RAM
through a 32 bit bus. Therefore for transfer between the high order 16 bits of the DTC and the internal
RAM, trace information cannot be acquired and no break can be generated.
4.12 Bus State Controller
The H8S bus state controller has a programmable wait mode and a WAIT pin input mode. The
programmable wait mode is valid when the emulation memory or user (target or external) memory is
accessed, but input to the WAIT pin is only valid when the user memory is accessed. Input to the user
WAIT pin is always valid during refresh cycles.
4.13 I/O Ports
The H8S I/O ports can be used as peripheral module I/O pins or as an address/data bus, depending on
the operation mode or internal register settings. The I/O port pins are valid during execution & break
state. User can access or modify the I/O port pins (multiplexed with peripheral module I/O pins) with
the I/O and MEMORY window.
4.14 A/D Converter
The analogue I/O pins are connected to the user system directly from the H8S MCU. Thus the reading
are valid during the execution and break state. Connect the AVCC pin (the VCC pin for the A/D) and the
VREF (reference voltage pin) to the A/D and D/A conversion power supply and the reference power
supply on the user's system.
NOTE: AVCC and VREF pins must be connected to VCC pins when the A/D and D/A converters are not
used. The conversion precision on the emulator is lower than that of the actual MCU. This is mainly due
to the extra resistance and capacitance introduced in the cabling and printed circuit boards.
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