Bus Arbitration; Operation - Renesas H8S/2368 Series Hardware Manual

6.11

Bus Arbitration

This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration).
There are three bus masters—the CPU, DTC, and DMAC*—which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
Note: * Not supported by the H8S/2366.
6.11.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one
bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a
bus master receives the bus request acknowledge signal, it takes possession of the bus until that
signal is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC* > DTC > CPU (Low)
An internal bus access by internal bus masters and external bus release, a refresh when the CBRM
bit is 0 can be executed in parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
(High) Refresh > External bus release (Low)
(High) External bus release > External access by internal bus master (Low)
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Note: * Not supported by the H8S/2366.
Rev. 2.00, 05/03, page 194 of 820