Figure 5.2 Block Diagram Of Interrupts Irq15 To Irq0 - Renesas H8S/2158 User Manual

IRQn input or
ExIRQn* input
Notes: n = 15 to 0
* ExIRQn stands for ExIRQ15 to ExIRQ2.

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0

KIN9 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts KIN9 to KIN0 and WUE15
to WUE8 are requested by an input signal at pins KIN9 to KIN0 and WUE15 to WUE8. Interrupts
KIN9 to KIN0 and WUE15 to WUE8 have the following features:
• Interrupts KIN9 and KIN8, KIN7 to KIN0, and WUE15 to WUE8 each form a group. The
interrupt exception handling for an interrupt request from the same group is started at the same
vector address.
• Enabling or disabling of interrupt requests can be selected with the I bit in CCR.
• An interrupt is generated by a falling edge at pins KIN9 to KIN0 and WUE15 to WUE8.
• Enabling or disabling of interrupt requests KIN9 to KIN0 and WUE15 to WUE8 can be
selected using KMIMRA, KMIMR6, and WUEMR3.
• The status of interrupt requests KIN9 to KIN0 and WUE15 to WUE8 are not indicated.
The detection of KIN9 to KIN0 and WUE15 to WUE8 interrupts does not depend on whether the
relevant pin has been set for input or output. However, when a pin is used as an external interrupt
input pin, do not clear the corresponding port DDR to 0 to use the pin as an I/O pin for another
function.
A block diagram of interrupts KIN9 to KIN0 and WUE15 to WUE8 is shown in figure 5.3.
IRQnSCA, IRQnSCB
Edge/level
detection circuit
Clear signal
Section 5 Interrupt Controller
IRQnE
IRQnF
S Q
R
Rev. 3.00 Jan 25, 2006 page 85 of 872
IRQn interrupt
request
REJ09B0286-0300