Figure 3.4 Stack State After Completion Of Interrupt Exception Handling - Renesas H8/3847R Series Hardware Manual

SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Prior to start of interrupt
exception handling
Legend:
PC : Upper 8 bits of program counter (PC)
H
PC : Lower 8 bits of program counter (PC)
L
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
Ignored on return.
*

Figure 3.4 Stack State after Completion of Interrupt Exception Handling

Figure 3.5 shows a typical interrupt sequence.
Stack area
PC and CCR
saved to stack
SP (R7)
SP + 1
CCR
SP + 2
SP + 3
SP + 4
After completion of interrupt
exception handling
Rev. 6.00 Aug 04, 2006 page 111 of 680
Section 3 Exception Handling
CCR
*
PC
H
PC
L
Even address
REJ09B0145-0600