Interrupt Exception Handling; Trap Instruction Exception Handling - Renesas H8S/2100 Series Hardware Manual

5.4

Interrupt Exception Handling

Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to
WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt
with the highest priority. For details, see section 6, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved in the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
5.5

Trap Instruction Exception Handling

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved in the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 5.4 shows the status of CCR after execution of trap instruction exception handling.
Table 5.4 Status of CCR after Trap Instruction Exception Handling
Interrupt Control Mode
0
1
I
Set to 1
Set to 1
Section 5 Exception Handling
CCR
UI
Retains value prior to execution
Set to 1
Rev. 1.00 May 09, 2008 Page 93 of 954
REJ09B0462-0100