Interrupt Response Times - Renesas H8SX/1650 Hardware Manual

5.6.4

Interrupt Response Times

Table 5.4 shows interrupt response times – the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols for execution
states used in table 5.4 are explained in table 5.5.
The stack area in on-chip RAM enables high-speed processing.
Table 5.4 Interrupt Response Times
Execution State
Interrupt priority determination*
Number of states until executing
2
instruction ends*
PC, CCR, EXR stacking
Vector fetch
3
Instruction fetch*
4
Internal processing*
Total (using on-chip memory)
Notes: 1. Two states for an internal interrupt.
2. In the case of the MULXS or DIVXS instruction
3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.
4. Internal operation after interrupt acceptance or after vector fetch
5. Not available in this LSI.
6. When setting the SP value to 4n, the interrupt response time is S
2, the interrupt response time is 2·S
5
Normal Mode*
Interrupt Interrupt
Control Control
Mode 0 Mode 2
1
6
S to 2·S * 2·S
K K K
10 to 31 11 to 31
.
K
Section 5 Interrupt Controller
Advanced Mode
Interrupt Interrupt
Control Control
Mode 0 Mode 2
3
1 to 19 + 2·S
I
6
S to 2·S * 2·S
K K K
S
h
2·S
I
2
10 to 31 11 to 31
Rev.2.00 Jun. 28, 2007 Page 111 of 666
5
Maximum Mode*
Interrupt Interrupt
Control Control
Mode 0 Mode 2
2·S 2·S
K K
11 to 31 11 to 31
; when setting to 4n +
K
REJ09B0311-0200