Interrupt Response Times; Table 5.4 Interrupt Response Times - Renesas H8SX/1520 Series Hardware Manual

5.6.4

Interrupt Response Times

Table 5.4 shows interrupt response times – the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols for execution
states used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in on-
chip ROM and the stack area in on-chip RAM enables high-speed processing.
Table 5.4
Execution State
Interrupt priority decision*
Number of states until executing
instruction ends*
PC, CCR, EXR stacking
Vector fetch
Instruction fetch*
Internal processing*
Total (using on-chip memory)
Notes: 1. Two states for an internal interrupt.
2. In the case of the MULXS or DIVXS instruction
3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.
4. Internal operation after interrupt acceptance or after vector fetch
5. Not available in this LSI.
6. When setting the SP value to 4n, the interrupt response time is S
2, the interrupt response time is 2·S
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Interrupt Response Times
Normal Mode*
Interrupt
Control
Mode 0
1
2
S to 2·S
K
3
4
10 to 31
5
Advanced Mode
Interrupt Interrupt
Control Control
Mode 2 Mode 0
1 to 19 + 2·S
6
2·S S to 2·S
*
K K K
11 to 31 10 to 31
.
K
Section 5 Interrupt Controller
Maximum Mode
Interrupt Interrupt
Control Control
Mode 2 Mode 0
3
I
6
2·S 2·S
*
K K K
S
h
2·S
I
2
11 to 31 11 to 31
; when setting to 4n +
K
Rev. 3.00 Mar. 14, 2006 Page 117 of 804
REJ09B0104-0300
5
Interrupt
Control
Mode 2
2·S
K
11 to 31