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5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4
Interrupt Response Times
No.
Execution Status
1
Interrupt priority determination*
2
Number of wait states until executing
instruction ends*
3
PC, CCR, EXR stack save
4
Vector fetch
5
Instruction fetch*
6
Internal processing*
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
5. Not available in this LSI.
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses
Symbol
Instruction fetch S
I
Branch address read S
Stack manipulation S
[Legend]
m: Number of wait states in an external device access.
1
2
3
4
Internal
Memory
1
J
K
5
Normal Mode*
Interrupt
Interrupt
control
control
mode 0
mode 2
3
3
1 to 19 +2·S
1 to 19+2·S
I
2·S
3·S
K
K
S
S
I
I
2·S
2·S
I
I
2
2
11 to 31
12 to 32
Object of Access
External Device
8 Bit Bus
2-State
3-State
Access
Access
4
6+2m
Advanced Mode
Interrupt
Interrupt
control
control
mode 0
mode 2
3
3
1 to 19+2·S
1 to 19+2·S
I
I
2·S
3·S
K
2·S
2·S
I
2·S
2·S
I
2
2
12 to 32
13 to 33
16 Bit Bus
2-State
3-State
Access
Access
2
3+m
Rev. 1.00, 09/03, page 87 of 704
I
K
I
I
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