Interrupt Response Times - Renesas H8S Series Hardware Manual

5.4.5

Interrupt Response Times

The H8S/2357 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in
on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the
first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 5-
10.
Table 5-9 Interrupt Response Times
No. Execution Status
1 Interrupt priority determination*
2 Number of wait states until executing
instruction ends*
3 PC, CCR, EXR stack save
4 Vector fetch
5 Instruction fetch*
6 Internal processing*
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend:
m: Number of wait states in an external device access.
Rev.6.00 Oct.28.2004 page 98 of 1016
REJ09B0138-0600H
1
2
3
4
Internal
Memory
S 1
I
S
J
S
K
Advanced Mode
INTM1 = 0
3
1 to (19+2·S )
I
2·S
K
2·S
I
2·S
I
2
12 to 32
Object of Access
External Device
8-Bit Bus
2-State 3-State
Access Access
4 6 + 2m
INTM1 = 1
3
1 to (19+2·S )
I
3·S
K
2·S
I
2·S
I
2
13 to 33
16-Bit Bus
2-State 3-State
Access Access
2 3 + m