Interrupt Response Times - Renesas H8S/2100 Series Hardware Manual

5.6.4

Interrupt Response Times

Table 5.10 shows interrupt response times − the intervals between generation of an interrupt
request and execution of the first instruction in the interrupt handling routine.
Table 5.10 Interrupt Response Times
No. Execution Status
1 Interrupt priority determination*
2 Number of wait states until executing instruction
2
ends*
3 Saving of PC and CCR in stack
4 Vector fetch
5 Instruction fetch*
6 Internal processing*
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
1
3
4
Section 5 Interrupt Controller
Advanced Mode
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Rev. 1.00 Apr. 28, 2008 Page 125 of 994
REJ09B0452-0100