Interrupt Response Times - Renesas Hitachi H8S/2194 Series Hardware Manual

6.4.5

Interrupt Response Times

Table 6.8 shows interrupt response times-the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols used in table
6.8 are explained in table 6.9.
Table 6.8 Interrupt Response Times
No. Number of States
1 Interrupt priority determination
2 Number of wait states until executing instruction ends
3 PC, CCR stack save
4 Vector fetch
5 Instruction fetch
6 Internal processing
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector
fetch.
Table 6.9 Number of States in Interrupt Handling Routine Execution
Symbol
Instruction fetch SI
Branch address read SJ
Stack manipulation SK
*1
*3
*4
Object of Access
Internal Memory
1
Advanced Mode
3
*2
1 to 19+2⋅S
I
2⋅S
k
2⋅S
I
2⋅S
I
2
12 to 32
Rev. 2.0, 11/00, page 119 of 1037