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Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.7 shows interrupt response times—the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.7 are explained in table 5.8.
Table 5.7
Interrupt Response Times
No. Execution Status
Interrupt priority determination *
1
2
Number of wait states until executing instruction
ends *
2
3
PC, CCR stack save
4
Vector fetch
Instruction fetch *
5
Internal processing *
6
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.8
Number of States in Interrupt Handling Routine Execution Status
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend:
m: Number of wait states in external device access.
Rev. 3.00 Jan 25, 2006 page 98 of 872
REJ09B0286-0300
1
3
4
Internal
Memory
S
1
I
S
J
S
K
Normal Mode
3
1 to (19 + 2·S
)
I
2·S
K
S
I
2·S
I
2
11 to 31
Object of Access
External Device
8-Bit Bus
2-State
3-State
Access
Access
4
6 + 2m
Advanced Mode
3
1 to (19 + 2·S
)
I
2·S
K
2·S
I
2·S
I
2
12 to 32
16-Bit Bus
2-State
3-State
Access
Access
2
3 + m
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