Computational Units - Analog Devices adsp-2100 Manual

1 Introduction
Data
Address
Generator
#1
Input Regs
ALU
Output Regs
Figure 1.1 Base Architecture
1.2.1

Computational Units

Every processor in the ADSP-2100 family contains three independent, full-
function computational units: an arithmetic/logic unit (ALU), a
multiplier/accumulator (MAC) and a barrel shifter. The computation
units process 16-bit data directly and provide hardware support for
multiprecision computation as well.
The ALU performs a standard set of arithmetic and logic operations in
addition to division primitives. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations. The shifter performs
logical and arithmetic shifts, normalization, denormalization, and derive-
exponent operations. The shifter implements numeric format control
including multiword floating-point representations. The computational
units are arranged side-by-side instead of serially so that the output of any
unit may be the input of any unit on the next cycle. The internal result (R)
bus directly connects the computational units to make this possible.
1 – 6
Data
Address
Generator
#2
Input Regs
MAC
Output Regs
16
R BUS
Program
Sequencer
14
14
24
16
Input Regs
Shifter
Output Regs
PMA BUS
DMA BUS
PMD BUS
DMD BUS