Other Interrupt Registers; Ilat Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Other Interrupt Registers

The interrupt controller includes three interrupt registers:
• registers –
ILAT
• registers –
IMASK
• registers –
PMASK
The ,
IMASK ILAT
described in the "Programmer Sequencer" chapter of the ADSP-TS101
TigerSHARC Processor Programming Reference.

ILAT Register

The register is a single 64-bit register accessed as two 32-bit registers,
ILAT
and
ILATL ILATH
occurs, the corresponding bit is set. The order of interrupt bits is the
interrupt priority—Bit0 is the lowest priority. See "IMASK Register" on
page 2-19 for bit assignments.
An application may emulate an interrupt by writing to the
set address (
ILATSTL
register to the OR of the old value and the written value. As a result,
ILAT
every set bit in the written data sets the corresponding bit in the
ister. Setting an interrupt bit causes the TigerSHARC processor to assume
the corresponding interrupt has occurred.
Interrupt bits can also be cleared by writing to the clear addresses (
or ). Such a write ANDs the data written with the old data of the
ILATCLH
register. In this case, a zero bit in the input data clears the corre-
ILAT
sponding bit in
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and
ILATH ILATL
and
IMASKH
and
PMASKH
, and registers all have the same bit definitions as
PMASK
. Each bit is dedicated to an interrupt—when an interrupt
or ). Writing to these addresses updates the
ILATSTH
, while a set bit keeps it unchanged. This way, an
ILAT
IMASKL
PMASKL
Interrupts
register
ILAT
reg-
ILAT
ILATCLL
4-11