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Reset and Powerup
When L1 instruction memory is configured as cache, make sure the sys-
tem software reset sequence has been read into the cache.
After either the watchdog or system software reset is initiated, the proces-
sor ensures that all asynchronous peripherals have recognized and
completed a reset.
For a reset generated by the watchdog timer, the processors transitions
into the boot mode sequence. The boot mode is configured by the state of
the
and the no boot on software reset control bits.
BMODE
If the no boot on software reset bit in
is determined by the
Software Reset Register (SWRST)
A software reset can be initiated by setting bits [2:0] in the system soft-
ware reset field in the software reset register (
determine whether the reset source was core double fault. A core double
fault reset resets both the core and the peripherals, excluding the RTC
block and most of the DPMC. Bit 15 indicates whether a software reset
has occurred since the last time
tively, indicate whether the software watchdog timer or a core double fault
has generated a software reset. Bits [15:13] are read-only and cleared when
the register is read. Bits [3:0] are read/write.
When the
BMODE
reset bit in
SYSCR
on-chip L1 memory. In this configuration, the core begins fetching
instructions from the beginning of on-chip L1 memory.
When the
BMODE
tions from address 0x2000 0000 (the beginning of async bank 0).
19-6
control bits.
BMODE
SWRST
pins are not set to b#000 and the no boot on software
is set, the processor starts executing from the start of
pins are set to b#000 the core begins fetching instruc-
ADSP-BF537 Blackfin Processor Hardware Reference
is cleared, the reset sequence
SYSCR
). Bit 3 can be read to
SWRST
was read. Bit 14 and bit 13, respec-
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