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RZ Family / RZ/G, RZ/A Series
2.6
Clock Configuration
Figure 2.7 shows a block diagram of the Clock configuration.
NOTE
SD Interface supports UHS-I mode of 50MB/s (SDR50) and 104MB/s (SDR104).
Clock IC
CLKINB_X1
X1
24MHz
CLKIN_X2
Figure 2.7
Block Diagram of Clock Configuration
R01UH0990EJ0101
Rev.1.01
Jul 28, 2022
Max. 125MHz
DIFF1
Max. 125MHz
DIFF1B
11.2896MHz
SE2
RZ/G2UL
24MHz
REF
EXCLK
11.2896MHz
SE1
AUDIO_CLK1
12.2880MHz
DIFF2
AUDIO_CLK2
DDR_CLK_P
DDR_CLK_N
TCK/SWDCLK
SD0_CLK
QSPI0_SPCLK
SD1_CLK
CSI_CLK_P
CSI_CLK_N
RIIC1_SCL
RIIC0_SCL
SSI1_BCK
RSPI1_CK
RZ/G2UL SMARC Module Board
RZ/Five SMARC Module Board
Ethernet0 PHY
XI
Ethernet1 PHY
XI
DDR4_SDRAM
CK_T
Max. 800MHz
CK_C
JTAG
20MHz
CLK
eMMC memory
Max.133MHz
CLK
Max. 33.33MHz
SD0 card slot
(SDR 3.3V)
CLK
Max. 66MHz
QSPI flash memory
(SDR mode)
VCC
Max. 100MHz
OctaFlash
(SDR mode)
VCC
OctaRAM
VCC
Max. 33.33MHz (SDR 3.3V)
Max. 1.5GHz
Max. 1MHz
Max. 1MHz
Max. 12.5MHz
Max. 10MHz
2. Functional Specifications
RZ/A3UL SMARC Module Board
QSPI Edition
RZ/A3UL SMARC Module Board
OCTAL Edition
Audio Codec
MCLK
BCLK
SCLK
SD1 card slot
XI
Camera connector
MIPI_CLK_P
MIPI_CLK_N
CAM_I2C_SCL
HDMI transceiver
DRXC_P
DRXC_N
SCLK/MCLK
SCL
CECCLK
CMOS Oscillator
12MHz
CLK
PMOD0
SCK
PMOD1
SCL
Note:
shows the Carrier Board
Page 49 of 83
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