Self Test Libraries Introduction; Cpu Registers; Invariable Memory; Variable Memory - Renesas RL78 Series Application Note

RL78 Family
1.

Self Test Libraries Introduction

The self test library (STL) provides self test functions covering the CPU registers, internal memory and system clock.
The library test harness provides an Application Programmers Interface (API) for each of the self test modules, which
are described in this applications note. These can be used in customer's application wherever required.
For the purposes of VDE certification, the self test library functions are built as separate modules. The IAR Embedded
Workbench test harness allows each of the tests functions to be selected in turn and run as a stand alone function. In
order to minimise the affects of the optimisation in the C compiler and minimise resources used, all of the self test
library files have been written in assembler. The default build of the test harness C files has been built with the
optimisation set to "None" in the IAR Embedded workbench.
All of the STL modules and test harness files are MISRA-C compliant
The system hardware requirements include that at least two independent clock sources are available, e.g. Crystal /
ceramic oscillator and an independent oscillator or external input source. The requirement is needed to provide an
independent clock reference for monitoring the system clock. The RL78 is able to provide these using the High speed
and Low speed internal oscillators which are independent of each other.
Equally the application can provide a more accurate external reference clock or external crystal/resonators for the main
system clock can equally be used.
fin fin
The following CPU self test functions are included in the RL78 self test library.
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CPU Registers

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Invariable Memory

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Variable Memory

•

System Clock

R01AN0749EG0201 Rev.2.01
Mar 04, 2014
Application Application
Software Software
HS HS
Oscillator Oscillator
Figure 1 Self Test Library (STL) Configuration
The following CPU registers tests are included in this library
All CPU working Registers in all four register banks, Stack Pointer (SP), Processor Status
word (PSW), Extension registers ES and CS.
Internal data path are verified as part of the correct operation of these register tests
IEC Reference - IEC 60730: 1999+A1:2003 Annex H - Table H.11.12.7
This tests the MCU internal Flash memory
IEC Reference - IEC 60730: 1999+A1:2003 Annex H - Table H.11.12.7
This tests the Internal SRAM memory
IEC Reference - IEC 60730: 1999+A1:2003 Annex H - Table H.11.12.7
Verifies the system clock operation and correct frequency against a reference clock source
IEC Reference - IEC 60730: 1999+A1:2003 Annex H - Table H.11.12.7
VDE Certified IEC60730/60335 Self Test Library
Call Call
Return Return
STL STL
Sub Sub
LS LS
Clock Clock
Oscillator Oscillator
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