Refresh Timer Control/Status Register (Rtmcsr) - Renesas H8/3067 Series User Manual

Section 6 Bus Controller
6.2.9

Refresh Timer Control/Status Register (RTMCSR)

7
Bit
CMF
Initial value 0
Read/Write R(W)*
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When
the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.
Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are
initialized to 0 by a reset and in hardware standby mode; they are not initialized in software
standby mode.
Note: Only 0 can be written to clear the flag.
Bit 7—Compare Match Flag (CMF): Status flag that indicates a match between the values of
RTCNT and RTCOR.
Bit 7
CMF Description
0 Clearing conditions
When the chip is reset and in standby mode
Read CMF when CMF = 1, then write 0 in CMF
1 Setting condition
When RTCNT = RTCOR
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
any of areas 2 to 5 is designated as DRAM space.
Bit 6
CMIE Description
0 The CMI interrupt requested by CMF is disabled
1 The CMI interrupt requested by CMF is enabled
Rev. 4.00 Jan 26, 2006 page 140 of 938
REJ09B0276-0400
6 5
CMIE CKS2
0 0
R/W R/W
4 3
CKS1
CKS0
0 0
R/W R/W
2 1
— —
1 1
— —
(Initial value)
(Initial value)
0
—
1
—