Timer Input Capture Control Register (Ticcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.7

Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are
cascaded. This module has one TICCR in channel 1.
Bit Bit Name
7 to 4 —
3 I2BE
2 I2AE
1 I1BE
0 I1AE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
- -
Initial value:
0 0
R/W:
R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Input Capture Enable
Specifies whether to include the TIOC2B pin in the TGRB_1 input capture
conditions.
0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions
1: Includes the TIOC2B pin in the TGRB_1 input capture conditions
0 R/W Input Capture Enable
Specifies whether to include the TIOC2A pin in the TGRA_1 input capture
conditions.
0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions
1: Includes the TIOC2A pin in the TGRA_1 input capture conditions
0 R/W Input Capture Enable
Specifies whether to include the TIOC1B pin in the TGRB_2 input capture
conditions.
0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions
1: Includes the TIOC1B pin in the TGRB_2 input capture conditions
0 R/W Input Capture Enable
Specifies whether to include the TIOC1A pin in the TGRA_2 input capture
conditions.
0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions
1: Includes the TIOC1A pin in the TGRA_2 input capture conditions
5 4 3 2 1
- - I2BE I2AE I1BE
0 0 0 0 0
R R R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
I1AE
0
R/W
10-37