Timer Input Select Register (Tisr); Operation; Pulse Output; Figure 11.3 Pulse Output Example - Renesas H8S/2437 Hardware Manual

11.3.9

Timer Input Select Register (TISR)

TISR selects a signal source of external clock/reset input for the counter.
Bit Bit Name Initial Value R/W
7 to 1 
All 1
0 IS 0
11.4

Operation

11.4.1

Pulse Output

Figure 11.3 shows an example for outputting an arbitrary duty pulse.
1. Clear the CCLR1 bit in TCR to 0 and then set the CCLR0 bit to 1 so that TCNT is cleared
according to the compare match of TCORA.
2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match
of TCORA and 0 is output according to the compare match of TCORB.
According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width
can be output without the intervention of software.
H'FF
TCORA
TCORB
H'00
TMO
Description
R/(W) Reserved
The initial value should not be changed.
R/W Input Select
Selects the internal synchronization signal (IVG signal)
or timer clock/reset input pin (TMIY or ExTMIY) as the
signal source of the external clock/reset input for the
TMRY counter.
0: IVG signal is selected
1: TMIY is selected
TCNT

Figure 11.3 Pulse Output Example

Counter clear
Rev. 1.00, 09/03, page 283 of 704