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7700 FAMILY
Renesas 7700 FAMILY Manuals
Manuals and User Guides for Renesas 7700 FAMILY. We have
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Renesas 7700 FAMILY manual available for free PDF download: User Manual
Renesas 7700 FAMILY User Manual (540 pages)
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.54 MB
Table of Contents
Table of Contents
4
Chapter 1 . Description
12
Performance Overview
12
Pin Configuration
12
Pin Description
12
Block Diagram
12
Chapter 2. Central Processing Unit (Cpu)
20
Accumulator (Acc)
21
Index Register X (X)
21
Index Register y (Y)
21
Stack Pointer (S)
21
Program Counter (PC)
23
Program Bank Register (PG)
23
Data Bank Register (DT)
25
Direct Page Register (DPR)
25
Processor Status Register (PS)
27
Bus Interface Unit
29
Overview
29
Functions of Bus Interface Unit (BIU)
31
Operation of Bus Interface Unit (BIU)
34
Access Space
36
Banks
37
Direct Page
37
Memory Assignment
38
Memory Assignment in Internal Area
38
Processor Modes
41
Single-Chip Mode
42
Memory Expansion and Microprocessor Modes
42
Setting Processor Modes
45
[Precautions When Operating in Single-Chip Mode]
47
Chapter 3 INPUT/OUTPUT PINS
48
Programmable I/O Ports
48
Direction Register
50
Port Register
51
I/O Pins of Internal Peripheral Devices
55
Chapter 4. Interrupts
56
Overview
56
Interrupt Sources
56
Interrupt Control
56
Interrupt Disable Flag (I)
61
Interrupt Request Bit
61
Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL)
63
Interrupt Priority Level
65
Interrupt Priority Level Detection Circuit
66
Interrupt Priority Level Detection Time
68
Sequence from Acceptance of Interrupt Request to Execution of Interrupt Routine
69
Change in IPL at Acceptance of Interrupt Request
71
Storing Registers
72
Return from Interrupt Routine
73
Multiple Interrupts
73
External Interrupts (INT
75
Function of INT
78
I Interrupt Request Bit
78
Switch of Occurrence Factor of INT
80
I Interrupt Request
80
Chapter 5 . Timer a
82
Overview
82
Block Description
82
Counter and Reload Register (Timer Ai Register)
85
Count Start Register
86
Timer Ai Mode Register
87
Timer Ai Interrupt Control Register
88
Port P5 and Port P6 Direction Registers
89
Timer Mode
90
Setting for Timer Mode
92
Count Source
94
Operation in Timer Mode
95
Select Function
96
Event Counter Mode
100
Setting for Event Counter Mode
103
Operation in Event Counter Mode
105
Select Functions
107
One-Shot Pulse Mode
111
Setting for One-Shot Pulse Mode
113
Count Source
115
Trigger
116
Operation in One-Shot Pulse Mode
117
Pulse Width Modulation (PWM) Mode
120
Setting for PWM Mode
122
Count Source
124
Trigger
124
Operation in PWM Mode
125
Chapter 6 . Timer B
130
Overview
130
Block Description
130
Counter and Reload Register (Timer Bi Register)
132
Count Start Register
133
Timer Bi Mode Register
134
Timer Bi Interrupt Control Register
135
Port P6 Direction Register
136
Timer Mode
137
Setting for Timer Mode
139
Count Source
140
Operation in Timer Mode
141
Event Counter Mode
143
Setting for Event Counter Mode
145
Operation in Event Counter Mode
146
Pulse Period/Pulse Width Measurement Mode
148
Setting for Pulse Period/Pulse Width Measurement Mode
150
Count Source
152
Operation in Pulse Period/Pulse Width Measurement Mode
153
Chapter 7 . Serial I/O
158
Overview
158
Block Description
158
Uarti Transmit/Receive Mode Register
161
Uarti Transmit/Receive Control Register 1
163
Uarti Transmit/Receive Control Register 1
164
Uarti Transmit Register and Uarti Transmit Buffer Register
166
Uarti Receive Register and Uarti Receive Buffer Register
168
Uarti Baud Rate Register (Brgi)
170
Uarti Transmit Interrupt Control and Uarti Receive Interrupt Control Registers
171
Port P8 Direction Register
173
Clock Synchronous Serial I/O Mode
174
Transfer Clock (Synchronizing Clock)
175
Transfer Data Format
176
Method of Transmission
177
Transmit Operation
181
Method of Reception
183
Receive Operation
187
Process on Detecting Overrun Error
190
Clock Asynchronous Serial I/O (UART) Mode
192
Transfer Rate (Frequency of Transfer Clock)
193
Transfer Data Format
195
Method of Transmission
197
Transmit Operation
201
Method of Reception
203
Receive Operation
206
Process on Detecting Error
208
Sleep Mode
209
Chapter 8 . A-D Converter
210
Overview
210
Block Description
210
A-D Control Register 0
212
A-D Control Register 1
213
A-D Control Register 1
215
A-D Register I (I = 0 to 7)
216
A-D Conversion Interrupt Control Register
217
Port P7 Direction Register
218
A-D Conversion Method (Successive Approximation Conversion Method)
219
Absolute Accuracy and Differential Non-Linearity Error
222
Absolute Accuracy
222
Differential Non-Linearity Error
223
Comparison Voltage in 8-Bit Mode
224
One-Shot Mode
225
Settings for One-Shot Mode
225
One-Shot Mode Operation Description
227
Repeat Mode
229
Settings for Repeat Mode
229
Repeat Mode Operation Description
231
Single Sweep Mode
232
Settings for Single Sweep Mode
232
Single Sweep Mode Operation Description
234
Repeat Sweep Mode 0
236
Settings for Repeat Sweep Mode 0
236
Repeat Sweep Mode 0 Operation Description
238
Repeat Sweep Mode 1
238
Settings for Repeat Sweep Mode 1
240
Repeat Sweep Mode 1 Operation Description
243
Chapter 9 . Watchdog Timer
246
Block Description
246
Watchdog Timer
246
Watchdog Timer Frequency Select Register
249
Operation Description
250
Basic Operation
250
Operation in Stop Mode
252
Operation in Hold State
252
Precautions When Using Watchdog Timer
253
Chapter 10. Stop Mode
254
Clock Generating Circuit
254
Operation Description
256
Termination by Interrupt Request Occurrence
257
Termination by Hardware Reset
258
Precautions for Stop Mode
259
Chapter 11. Wait Mode
260
Clock Generating Circuit
260
Operation Description
260
Termination by Interrupt Request Occurrence
263
Termination by Hardware Reset
263
Precautions for Wait Mode
264
Chapter 12 . Connection with External Devices
266
Signals Required for Accessing External Devices
266
Descriptions of Signals
267
Operation of Bus Interface Unit (BIU)
273
Bus Cycle
276
Ready Function
279
Operation Description
280
Hold Function
283
Operation Description
284
Chapter 13. Reset
290
Hardware Reset
290
Pin State
292
State of CPU, SFR Area, and Internal RAM Area
293
Internal Processing Sequence after Reset
298
Time Supplying "L" Level to RESET Pin
299
Software Reset
301
Chapter 14 . Clock Generating Circuit
302
Oscillation Circuit Example
302
Connection Example Using Resonator/Oscillator
303
Input Example of Externally Generated Clock
303
Clock
304
Clock Generated in Clock Generating Circuit
305
Operation Clock for Internal Peripheral Devices
306
Chapter 15. Electrical Characteristics
308
Absolute Maximum Ratings
308
Electrical Characteristics
309
A-D Converter Characteristics
312
Internal Peripheral Devices
315
Ready and Hold
320
Single-Chip Mode
323
Memory Expansion Mode and Microprocessor Mode : When 2- Φ Access in
325
Memory Expansion Mode and Microprocessor Mode : When 3- Φ Access in
330
Memory Expansion Mode and Microprocessor Mode : When 4- Φ Access in
335
High-Speed Running
340
High-Speed Running
345
Memory Expansion Mode and Microprocessor Mode : When 5- Φ Access in
350
High-Speed Running (Internal RAM Access)
355
Testing Circuit for Ports P0 to P8, Φ
358
And E
358
Chapter 16. Standard Characteristics
360
Standard Characteristics
360
Programmable I/O Port (CMOS Output) Standard Characteristics
361
ICC-F
362
A-D Converter Standard Characteristics
363
Chapter 17. Applications
366
Memory Expansion
366
Memory Expansion Model
367
How to Calculate Timing
369
Points in Memory Expansion
373
Example of Memory Expansion
391
Example of I/O Expansion
402
Chapter 18. Prom Version
406
EPROM Mode
406
Pin Description
408
Programming Algorithm of Built-In PROM
412
Electrical Characteristics of Programming Algorithm
414
Usage Precaution
415
Precautions on All PROM Versions
415
Precautions on One Time PROM Version
416
Precautions on EPROM Version
416
Chapter 19. Flash Memory Version
418
Parallel Input/Output Mode
418
Pin Description
421
Access to Built–In Flash Memory
422
Read–Only Mode
424
Read/Write (Software Command Control) Mode
426
Electrical Characteristics
435
Program/Erase Algorithm Flow Chart
437
Serial Input/Output Mode
438
Pin Description
438
Access to Built-In Flash Memory
440
Electrical Characteristics
448
Program Algorithm Flow Chart
450
Appendix
452
Appendix 1. Memory Assignment
452
Appendix 2. Memory Assignment in SFR Area
452
Appendix 3. Control Registers
452
Appendix 4. Package Outlines
452
Interrupt Control Register
482
Appendix 5. Example for Processing Unused Pins
485
Appendix 6. Hexadecimal Instruction Code Table
488
Appendix 7. Machine Instructions
491
Appendix 8. Examples of Noise Immunity Improvement
512
Appendix 9. Q & a
522
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