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7.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS
bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR,
DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Figure 7-9 shows the memory map for chain transfer.
DTC vector
Register information
address
start address
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Register information
Register information
Figure 7-9 Chain Transfer Memory Map
CHNE = 1
CHNE = 0
Rev. 5.00, 12/03, page 205 of 1088
Source
Destination
Source
Destination
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