Timing Of Counter Clear At Compare-Match; Tcnt External Reset Timing; Timing Of Overflow Flag (Ovf) Setting; Figure 11.8 Timing Of Counter Clear By Compare-Match - Renesas H8S/2437 Hardware Manual

11.5.4

Timing of Counter Clear at Compare-Match

TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 11.8 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
TCNT

Figure 11.8 Timing of Counter Clear by Compare-Match

11.5.5

TCNT External Reset Timing

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
11.9 shows the timing of clearing the counter by an external reset input.
φ
External reset
input pin
Clear signal
TCNT

Figure 11.9 Timing of Counter Clear by External Reset Input

11.5.6

Timing of Overflow Flag (OVF) Setting

The OVF flag in TCSR is set to 1 by an overflow signal output when the TCNT overflows
(changes from H'FF to H'00). Figure 11.10 shows the timing of OVF flag setting.
Rev. 1.00, 09/03, page 286 of 704
N
N – 1
H'00
N H'00