Page 1 Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
Page 3 Hitachi 16-Bit Single-Chip Microcomputer H8S/2194 Series, H8S/2194C Series, ™ ™ H8S/2194 F-ZTAT , H8S/2194C F-ZTAT H8S/2194, HD6432194, HD64F2194, H8S/2193, HD6432193 H8S/2192, HD6432192 H8S/2191, HD6432191 H8S/2194C, HD6432194C, HD64F2194C, H8S/2194B, HD6432194B H8S/2194A, HD6432194A Hardware Manual ADE-602-160A Rev. 2.0 11/10/00 Hitachi, Ltd.
Page 4 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 5 Main Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) All pages of Amendments due to introduction of the H8S/2194C this manual series 1.1 Overview Table 1.1 Features Memory and Product lineup amended Differences between Added H8S/2194C Series and H8S/2194 Series All pages of...
Page 6 Page Item Revisions (See Manual for Details) 7.3.2 Flash Memory Control Description amended Register 2 (FLMCR2) The ESU and PSU bits are cleared to 0 in power- down state (excluding the medium-speed mode, module stop mode, and sleep mode), hardware protect mode, and software protect mode.
Page 7 Page Item Revisions (See Manual for Details) 7.8.9 Programmer Mode Figure 7.23 Oscillation Stabilization Time, Boot Transition Time Program Transfer Time, and Power Supply Fall Sequence Vcc timing amended Added 7.10 Note on Switching from F-ZTAT Version to Mask ROM Version ...
Page 8 Page Item Revisions (See Manual for Details) 547 to 549 Description amended 25.3.2 Master Transmit Operation 550 to 552 25.3.3 Master Receive Operation 25.3.5 Slave Transmit Operation 25.3.8 Sample Flowcharts Figure 25.14 Flowchart for Master Transmit Mode (Example) amended Figure 25.15 Flowchart for Master Receive Mode (Example) amended 565, 566 25.3.9 Initialization of Internal...
Page 9 Page Item Revisions (See Manual for Details) 28.8.4 Register Descriptions (5) Capstan Speed Error Detection Control Register (CFVCR) Descriptions of bits 1 and 0 amended 28.12.5 Additional V Pulse Figure 28.46 Additional V Pulse Negative Polarity Signal is Specified Value of POL amended 28.13.5 Register Descriptions (8) Duty I/O Register (DI/O) Descriptions of ASM Mark Detect Mode amended 28.13.8 Duty Discriminator...
Page 10: Table Of Contents
Contents Section 1 Overview..................Overview ........................Internal Block Diagram ....................Pin Arrangement and Functions..................1.3.1 Pin Arrangement ..................... 1.3.2 Pin Functions....................Differences between H8S/2194C Series and H8S/2194 Series........14 Section 2 CPU ....................15 Overview ........................15 2.1.1 Features......................15 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.........
Page 11 Basic Timing ....................... 57 2.9.1 Overview ......................57 2.9.2 On-Chip Memory (ROM, RAM)..............57 2.9.3 On-Chip Supporting Module Access Timing............ 58 2.10 Usage Note ........................58 Section 3 MCU Operating Modes ..............59 Overview........................59 3.1.1 Operating Mode Selection ................59 3.1.2 Register Configuration..................
Page 12 4.9.2 Clearing Subactive Mode................. 85 4.10 Direct Transition......................86 4.10.1 Overview of Direct Transition ................. 86 Section 5 Exception Handling ................ 87 Overview ........................87 5.1.1 Exception Handling Types and Priority............87 5.1.2 Exception Handling Operation ................. 88 5.1.3 Exception Sources and Vector Table ..............88 Reset ...........................
Page 13 6.5.2 Instructions that Disable Interrupts..............121 6.5.3 Interrupts during Execution of EEPMOV Instruction........121 6.5.4 When NMI is Disabled ..................121 Section 7 ROM (H8S/2194 Series) ..............123 Overview........................123 7.1.1 Block Diagram ....................123 Overview of Flash Memory..................124 7.2.1 Features......................
Page 14 7.10 Note on Switching from F-ZTAT Version to Mask ROM Version......... 169 Section 8 ROM (H8S/2194C Series) .............. 171 Overview ........................171 8.1.1 Block Diagram ....................171 Overview of Flash Memory..................172 8.2.1 Features......................172 8.2.2 Block Diagram ....................173 8.2.3 Flash Memory Operating Modes..............
Page 15 8.8.9 Programmer Mode Transition Time ..............216 8.8.10 Notes On Memory Programming ..............216 Flash Memory Programming and Erasing Precautions ..........217 8.10 Note on Switching from F-ZTAT Version to Mask ROM Version ........ 219 Section 9 RAM....................221 Overview........................221 9.1.1 Block Diagram ....................
Page 16 11.3.4 Pin States ......................246 11.4 Port 2........................... 247 11.4.1 Overview......................247 11.4.2 Register Configuration..................247 11.4.3 Pin Functions....................251 11.4.4 Pin States ......................253 11.5 Port 3........................... 254 11.5.1 Overview......................254 11.5.2 Register Configuration..................254 11.5.3 Pin Functions....................258 11.5.4 Pin States ......................
Page 17 12.2 Descriptions of Respective Registers ................291 12.2.1 Timer Mode Register A (TMA) ............... 291 12.2.2 Timer Counter A (TCA) .................. 293 12.2.3 Module Stop Control Register (MSTPCR) ............293 12.3 Operation........................294 12.3.1 Operation as the Interval Timer................ 294 12.3.2 Operation of the Timer for Clocks..............
Page 18 14.3.2 8-bit Reload Timer (TMJ-2)................316 14.3.3 Remote Controlled Data Transmission ............. 317 Section 15 Timer L ..................321 15.1 Overview ........................321 15.1.1 Features......................321 15.1.2 Block Diagram ....................322 15.1.3 Register Configuration..................323 15.2 Descriptions of Respective Registers ................324 15.2.1 Timer L Mode Register (LMR)................
Page 19 16.5.2 Reeling Controls....................352 16.5.3 Slow Tracking Mono-multi Function ............... 352 16.5.4 Acceleration and Braking Processes of the Capstan Motor........ 353 Section 17 Timer X1..................355 17.1 Overview........................355 17.1.1 Features......................355 17.1.2 Block Diagram ....................356 17.1.3 Pin Configuration .................... 357 17.1.4 Register Configuration..................
Page 20 18.2.1 Watchdog Timer Counter (WTCNT)..............394 18.2.2 Watchdog Timer Control/Status Register (WTCSR)......... 394 18.2.3 System Control Register (SYSCR)..............397 18.2.4 Notes on Register Access................. 397 18.3 Operation........................399 18.3.1 Watchdog Timer Operation................399 18.3.2 Interval Timer Operation ................. 400 18.3.3 Timing of Setting of Overflow Flag (OVF) ............401 18.4 Interrupts ........................
Page 21 21.1.1 Features......................423 21.1.2 Block Diagram ....................424 21.1.3 Pin Configuration .................... 424 21.1.4 Register Configuration..................425 21.2 Register Descriptions ....................426 21.2.1 PWM Control Register (PWCR) ..............426 21.2.2 PWM Data Registers U and L (PWDRU, PWDRL).......... 427 21.2.3 Module Stop Control Register (MSTPCR) ............428 21.3 14-Bit PWM Operation ....................
Page 22 23.2.8 Bit Rate Register (BRR1) ................457 23.2.9 Serial Interface Mode Register (SCMR1) ............464 23.2.10 Module Stop Control Register (MSTPCR) ............465 23.3 Operation........................466 23.3.1 Overview......................466 23.3.2 Operation in Asynchronous Mode..............468 23.3.3 Multiprocessor Communication Function............478 23.3.4 Operation in Clock Synchronous Mode ............
Page 23 25.2.8 Module Stop Control Register (MSTPCR) ............545 25.3 Operation........................546 25.3.1 I C Bus Data Format..................546 25.3.2 Master Transmit Operation ................547 25.3.3 Master Receive Operation................550 25.3.4 Slave Receive Operation.................. 553 25.3.5 Slave Transmit Operation ................556 25.3.6 IRIC Setting Timing and SCL Control .............
Page 24 27.3.2 Enable ......................597 27.3.3 Bcc Instruction ....................597 27.3.4 BSR Instruction....................601 27.3.5 JSR Instruction ....................602 27.3.6 JMP Instruction ....................603 27.3.7 RTS Instruction ....................604 27.3.8 SLEEP Instruction................... 604 27.3.9 Competing Interrupt ..................607 Section 28 Servo Circuits................611 28.1 Overview ........................
Page 25 28.6.3 Register Configuration..................683 28.6.4 Register Descriptions..................684 28.6.5 Description of Operation ................. 689 28.6.6 f Correction in Trick Play Mode ..............691 28.7 Drum Phase Error Detector ..................692 28.7.1 Overview ......................692 28.7.2 Block Diagram ....................692 28.7.3 Register Configuration..................694 28.7.4 Register Descriptions..................
Page 26 28.13.1 Overview......................746 28.13.2 Block Diagram ....................747 28.13.3 Pin Configuration .................... 748 28.13.4 Register Configuration..................748 28.13.5 Register Descriptions..................749 28.13.6 Operation ......................763 28.13.7 CTL Input Section ................... 766 28.13.8 Duty Discriminator..................769 28.13.9 CTL Output Section..................775 28.13.10 Trapezoid Waveform Circuit.................
Page 27 29.3.1 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A ..........841 29.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A......847 29.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A ..........848 29.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A......
Page 28: Section 1 Overview
Section 1 Overview Overview The H8S/2194 Series, and H8S/2194C Series comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Page 29 Table 1.1 Features Item Specifications General-register architecture • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for real-time control • Maximum operating frequency: 10 MHz/4 to 5.5 V Operable by 32 kHz subclock •...
Page 30 Item Specifications Timer (4) Timer L • 8-bit up/down counter • Clock source can be selected among 2 types of internal clock, CFG frequency division signal, and PB and REC-CTL (control pulse) • Compare-match clearing function/auto reload function (5) Timer R •...
Page 31 Item Specifications Serial Two types of serial communication interface is incorporated communication (1) SCI1 interface (SCI) • Asynchronous mode or synchronous mode selectable • Desired bit rate selectable with built-in baud rate generator • Multiprocessor communication function (2) SCI2 • 32-byte data automatically transferrable •...
Page 32 Item Specifications • Memory Flash memory or mask ROM • High-speed static RAM Product Name H8S/2194C 256 kbytes 6 kbytes H8S/2194B 192 kbytes 6 kbytes H8S/2194A 160 kbytes 6 kbytes H8S/2194 128 kbytes 3 kbytes H8S/2193 112 kbytes 3 kbytes H8S/2192 96 kbytes 3 kbytes...
Page 33: Internal Block Diagram
Internal Block Diagram An internal block diagram of the chip is shown in figure 1.1. P37/TMO P27/SCK2 P36/BUZZ P26/SO2 P35/PWM3 P25/SI2 H8S/2000 CPU P34/PWM2 P24/SCL P33/PWM1 P23/SDA P32/PWM0 P22/SCK1 P31/STRB Internal data bus P21/SO1 P30/CS P20/SI1 R O M Internal address bus P17/TMOW P16/IC P46/FTOB...
Page 34: Pin Arrangement And Functions
Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangement of the chip is shown in figure 1.2. P73/PPG3 P12/IRQ2 P74/PPG4 P11/IRQ1 P10/IRQ0 P75/PPG5 P76/PPG6 P27/SCK2 P26/SO2 P77/PPG7 P25/SI2 P80/EXTTRG P24/SCL P81/EXCAP P23/SDA P82/SV1 P22/SCK1 P83/SV2 P21/SO1 P20/SI1 P37/TMO FP-112 Csync (Top view) AUDIO FF...
Page 35: Pin Functions
1.3.2 Pin Functions Table 1.2 summarizes the functions of the chip’s pins. Table 1.2 Pin Functions Type Symbol Pin No. Name and Function Power 45, 70, Input Power supply: supply 82, 109 All Vcc pins should be connected to the system power supply (+5V) 43, 68, Input...
Page 36 Type Symbol Pin No. Name and Function System Input Reset input: control When this pin is driven low, the chip is reset Input Flash memory enable: Enables/disables flash memory programming. This pin is available only with MCU with flash memory on-chip. For mask ROM type, do not connect anything to this pin ,54 Interrupts...
Page 37 Type Symbol Pin No. Name and Function ,54 Timers Input Timer R input capture: Input pin for input capture of Timer R TMRU-1 or TMRU-2 FTOA Output Timer X1 output compare A and B output: FTOB Output pin for output compare A and B of Timer FTIA Input Timer X1 input capture A, B, C and D input:...
Page 38 Type Symbol Pin No. Name and Function AN7 to 18 to 11 Input Analog input channels 7 to 0: converter Analog data input pins. A/D conversion is started by a software triggering Input Analog input channels 8, 9, A and B: Analog data input pins.
Page 39 Type Symbol Pin No. Name and Function Servo CTL Amp Output CTL amp output: circuits Output pin for CTL amp CTL SMT Input CTL Schmitt amp input: Input pin for CTL Schmitt amp CTLFB Input CLT feedback input: Input pin for CTL amp high-range characteristics control CTLREF Output...
Page 40 Type Symbol Pin No. Name and Function I/O port P07 to P00 11 to 18 Input Port 0: 8-bit input pins P17 to P10 61 to 54 Input Port 1: /output 8-bit I/O pins P27 to P20 53 to 46 Input Port 2: /output...
Page 41: Differences Between H8S/2194C Series And H8S/2194 Series
Differences between H8S/2194C Series and H8S/2194 Series Though the H8S/2194C series is compatible with the H8S/2194 series and their supporting modules are almost identical, there are some differences between them as shown below. For details, see the following sections. Table 1.3 Differences between H8S/2194C series and H8S/2194 series H8S/2194C Series H8S/2194 Series...
Page 42: Section 2 Cpu
Section 2 CPU Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
Page 43: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
16 ÷ 8-bit register-register divide: 1200 ns 16 × 16-bit register-register multiply: 2000 ns 32 ÷ 16-bit register-register divide: 2000 ns • Two CPU operating modes Normal mode*/Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available for this LSI.
Page 44: Differences From H8/300H Cpu
• Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing mode The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Page 45: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area).
Page 46 (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2.
Page 47 (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack.
Page 48 (d) Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
Page 49 (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack.
Page 50: Address Space
Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF...
Page 51: Register Configuration
Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR) 7 6 5 4 3 2 1 0 T –...
Page 52: General Registers
2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Page 53: Control Registers
Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
Page 54: Initial Register Values
Bit 6: User Bit or Interrupt Mask Bit (UI) Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, see section 6, Interrupt Controller.
Page 55: Data Formats
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4- bit BCD data.
Page 56 Data Type General Register Data format Word data Word data Longword data [Legend] : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.10 General Register Data Formats (2) Rev.
Page 57: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 58: Instruction Set
Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer , PUSH LDM, STM MOVFPE , MOVTPE Arithmetic ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS...
Page 59: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Instruction — — — — — — — POP, PUSH —...
Page 60: Table Of Instructions Classified By Function
2.6.3 Table of Instructions Classified by Function Table 2.3 to 2.10 summarize the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) (EAd) Destination operand (EAs)
Page 61 Table 2.3 Data Transfer Instructions Instruction Size Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register MOVFPE Cannot be used in this LSI MOVTPE Cannot be used in this LSI @SP+ →...
Page 62 Table 2.4 Arithmetic Instructions Instruction Size Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Page 63 Instruction Size Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another...
Page 64 Table 2.5 Logic Instructions Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data...
Page 65 Table 2.7 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register 0 →...
Page 66 Instruction Size Function C ⊕ (<bit-No.> of <EAd>) → C BOXR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C ⊕ [~ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in...
Page 67 Table 2.8 Branch Instructions Instruction Size Function  Branches to a specified address if a specified condition is true The branching conditions are listed below Mnemonic Description Condition BRA (BT) Always (True) Always BRN (BF) Never (False) Never HIgh CVZ = 0 Low of Same CVZ = 1 BCC (BHS)
Page 68 Table 2.9 System Control Instructions Instruction Size Function  TRAPA Starts trap-instruction exception handling  Returns from an exception-handling routine  SLEEP Causes a transition to a power-down state (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR.
Page 69 Table 2.10 Block Data Transfer Instructions Instruction Size Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+→@er6+ R4L−1→R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+→@er6+ R4−1→R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6 R4L or R4: size of block (bytes)
Page 70: Basic Instruction Formats
2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc.
Page 71: Notes On Use Of Bit-Manipulation Instructions
2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0.
Page 72: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 73 (4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn (a) Register indirect with post-increment–@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
Page 74 (6) Immediate–#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
Page 75: Effective Address Calculation
If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation...
Page 76 Table 2.13 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) 24 23 Don’t General register contents care Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) General register contents 24 23...
Page 77 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Absolute address @aa:8 24 23 Don’t H'FFFF care @aa:16 24 23 16 15 Sign Don’t exten- care sion @aa:24 24 23 Don’t care @aa:32 24 23 Don’t care Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data Program-counter relative @(d:8, PC)/@(d:16, PC)
Page 78 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Memory indirect @@aa:8 • Normal mode* H'000000 24 23 16 15 Don’t H'00 care Memory contents • Advanced mode H'000000 24 23 Don’t Memory contents care Note: Not available in this LSI. Rev.
Page 79: Processing States
Processing States 2.8.1 Overview The CPU has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response...
Page 80: Reset State
Program execution state Sleep mode External interrupt request Exception-handling state Standby mode Power-down state RES = High Reset state From any state, a transition to the reset state occurs whenever RES goes low. A transition can Notes: also be made to the reset state when the watchdog timer overflows. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc.
Page 81: Exception-Handling State
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions.
Page 82: Program Execution State
Advanced Mode Normal Mode (24 bits) (16 bits) Notes: 1. Ignored when returning. 2. Normal mode is not available for this LSI. Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. Rev.
Page 83: Power-Down State
2.8.5 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode.
Page 84: Basic Timing
Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two states.
Page 85: On-Chip Supporting Module Access Timing
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.18 shows the access timing for the on-chip supporting modules. Bus cycle Internal address bus Address...
Page 86: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection This LSI has one operating mode (mode 1). This mode is selected depending on settings of the mode pin (MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MCU Operating Mode CPU Operating Mode Description...
Page 87: Register Descriptions
Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : — — — — — — — MDS0 Initial value : —* — R/W : — — — — — — Note: * Determined by MD0 pin MDCR is an 8-bit read-only register monitors the current operating mode of this LSI. Bit 7 to 1: Reserved.
Page 88 Bits 5 and 4: Interrupt control modes 1 and 0 (INTM1, INTM0) These bits are for selecting the interrupt control mode of the interrupt controller. For details of the interrupt control modes, see section 6.4, Interrupt Operation. Bit 5 Bit 4 Interrupt INTM1 INTM0...
Page 89: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16 Mbyte address space in advanced mode. Rev. 2.0, 11/00, page 62 of 1037...
Page 90: Address Map
Address Map H8S/2191 H8S/2192 H'000000 H'000000 Vector area Vector area H'0000FF On-chip ROM On-chip ROM (96 kbytes) (80 kbytes) H'007FFF H'013FFF H'017FFF H'FF8000 H'FFD000 H'FFD000 Internal I/O register Internal I/O register H'FFD2FF H'FFD2FF H'FFF3B0 H'FFF3B0 On-chip RAM On-chip RAM (3kbytes) (3kbytes) H'FFFF00 H'FFFFAF...
Page 91 H8S/2193 H8S/2194 H'000000 H'000000 Vector area Vector area On-chip ROM On-chip ROM (112 kbytes) (128 kbytes) H'01BFFF H'01FFFF H'FFD000 H'FFD000 Internal I/O register Internal I/O register H'FFD2FF H'FFD2FF H'FFF3B0 H'FFF3B0 On-chip RAM On-chip RAM (3kbytes) (3kbytes) H'FFFFAF H'FFFFAF H'FFFFB0 H'FFFFB0 Internal I/O register Internal I/O register H'FFFFFF...
Page 92 H8S/2191A H8S/2194B H'000000 H'000000 Vector area Vector area H'0000FF On-chip ROM On-chip ROM (192 kbytes) (160 kbytes) H'007FFF H'027FFF H'02FFFF H'FF8000 H'FFD000 H'FFD000 Internal I/O register Internal I/O register H'FFD2FF H'FFD2FF H'FFE7B0 H'FFE7B0 On-chip RAM On-chip RAM (6 kbytes) (6 kbytes) H'FFFF00 H'FFFFAF H'FFFFAF...
Page 93 H8S/2194C H'000000 Vector area On-chip ROM (256 kbytes) H'03FFFF H'FFD000 Internal I/O register H'FFD2FF H'FFE7B0 On-chip RAM (6 kbytes) H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.4 Address Map (4) Rev. 2.0, 11/00, page 66 of 1037...
Page 94: Section 4 Power-Down State
Section 4 Power-Down State Overview In addition to the normal program execution state, this LSI has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 95 Table 4.1 Internal Chip States in Each Mode High- Medium- Module Function Speed Speed Sleep Stop Watch Subactive Subsleep Standby System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted Subclock pulse Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning generator Instructions Functioning Medium-...
Page 96 Reset state Program-halted state Program execution state Program-halted state SLEEP SLEEP instruction a Active instruction Sleep Standby (high-speed) (high-speed) mode Interrupt Interrupt mode mode SLEEP SLEEP instruction instruction SLEEP Interrupt instruction SLEEP SLEEP instruction Active Sleep instruction Interrupt (medium-speed) (medium-speed) mode mode SLEEP...
Page 97 Table 4.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before State after Transition State after Return Transition SSBY TMA3 LSON DTON by SLEEP Instruction by Interrupt High-speed Sleep High-speed /medium- /medium-speed speed   Standby High-speed /medium-speed ...
Page 98: Register Configuration
4.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR registers. Table 4.3 summarizes these registers. Table 4.3 Power-Down State Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'00 H'FFEA Low-power control register LPWRCR H'00 H'FFEB...
Page 99: Register Descriptions
Register Descriptions 4.2.1 Standby Control Register (SBYCR) Bit : SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value : — — R/W : SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset. Bit 7: Software Standby (SSBY) Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction.
Page 100 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Standby time = 16 states Notes: * Don't care...
Page 101: Low-Power Control Register (Lpwrcr)
4.2.2 Low-Power Control Register (LPWRCR) Bit : DTON LSON NESEL — — — Initial value : R/W : — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset. Bit 7: Direct-Transfer On Flag (DTON) Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a SLEEP instruction.
Page 102 Bit 6 LSON Description • When a SLEEP instruction is executed in high-speed mode or medium-speed mode, transition is made to sleep mode, standby mode, or watch mode • When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode •...
Page 103: Timer Register A (Tma)
4.2.3 Timer Register A (TMA) Bit : TMAOV TMAIE — — TMA3 TMA2 TMA1 TMA0 Initial value : R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. The timer register A (TMA) controls timer A interrupts and selects input clock. Only Bit 3 is explained here.
Page 104: Module Stop Control Register (Mstpcr)
4.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
Page 105: Medium-Speed Mode
Medium-Speed Mode When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The on-chip supporting modules other than the CPU always operate on the high-speed clock (φ).
Page 106: Sleep Mode
Sleep Mode 4.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules (excluding the servo circuit and 12-bit PWM) do not stop.
Page 107: Module Stop Mode
Module Stop Mode 4.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
Page 108: Standby Mode
Standby Mode 4.6.1 Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode is entered.
Page 109 Table 4.5 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 10 MHz 8 MHz Unit 8192 states 16384 states 32768 states 65536 states 131072 states 13.1 16.4 262144 states 26.2 32.8 µs 16 states : Recommended time setting Note: Don't care (2) Using an External Clock Any value can be set.
Page 110: Watch Mode
Watch Mode 4.7.1 Watch Mode If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to watch mode.
Page 111: Subsleep Mode
Subsleep Mode 4.8.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to subsleep mode.
Page 112: Subactive Mode
Subactive Mode 4.9.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, the CPU makes a transition to subactive mode.
Page 113: Direct Transition
4.10 Direct Transition 4.10.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program* is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
Page 114: Section 5 Exception Handling
Section 5 Exception Handling Overview 5.1.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 115: Exception Handling Operation
5.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: [1] The program counter (PC) and condition-code register (CCR) are pushed onto the stack. [2] The interrupt mask bits are updated. The T bit is cleared to 0. [3] A vector address corresponding to the exception source is generated, and program execution starts from that address.
Page 116 Table 5.2 Exception Vector Table Exception Source Vector Number Vector Address Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 Direct transition H'0018 to H001B External interrupt H'001C to H'001F Trap instruction (4 sources) H'0020 to H'0023...
Page 117: Reset
Reset 5.2.1 Overview A reset has the highest exception priority. When the pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set.
Page 118: Interrupts After Reset
Vector Internal Fetch of first program fetch processing instruction Internal address bus Internal read signal Internal write signal High level Internal data bus : Reset exception vector address ((1) = H'0000 or H'000000) : Start address (contents of reset exception vector address) : Start address ((3) = (2)) : First program instruction Figure 5.2 Reset Sequence (Mode 1)
Page 119: Interrupts
Interrupts Interrupt exception handling can be requested by seven external sources (NMI and IRQ5 to IRQ0) and internal sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI), A/D converter (ADC), I C bus interface (IIC), servo circuits, synchronized detection, address...
Page 120: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 121: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 5.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. CCR * (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 5.4 (1) Stack Status after Exception Handling (Normal Mode)* Note: * Normal mode is not available for this LSI.
Page 122: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, this chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 123 Rev. 2.0, 11/00, page 96 of 1037...
Page 124: Section 6 Interrupt Controller
Section 6 Interrupt Controller Overview 6.1.1 Features This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: (1) Two Interrupt Control Modes • Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Page 125: Block Diagram
6.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 6.1. INTM1, INTM0 SYSCR NMIEG1, NMIEG0 Interrupt request NM input NMI input unit Vector number IRQ input IRQ input unit IRQR Priority determina- tion I, UI IEGR IENR Internal...
Page 126: Pin Configuration
6.1.3 Pin Configuration Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Interrupt Controller Pins Name Symbol Function Nonmaskable Input Nonmaskable external interrupt; rising, falling, or interrupt both edges can be selected ,54 External interrupt Input Maskable external interrupts; rising, falling, or both request edges can be selected ,54...
Page 127: Register Descriptions
Register Descriptions 6.2.1 System Control Register (SYSCR) Bit : — — — INTM1 INTM0 XRST NMIEG1 NMIEG0 Initial value : — — — R/W : SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge for 10, .
Page 128: Interrupt Control Registers A To D (Icra To Icrd)
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) Bit : ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value : R/W : The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI.
Page 129: Irq Enable Register (Ienr)
6.2.3 IRQ Enable Register (IENR) Bit : — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value : — — R/W : IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IENR is initialized to H'00 by a reset. Bits 7 and 6: Reserved Do not write 1 to them.
Page 130: Irq Edge Select Registers (Iegr)
6.2.4 IRQ Edge Select Registers (IEGR) Bit : — IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 Initial value : R/W : — IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins ,54 to ,54 . IEGR register is initialized to H'00 by a reset.
Page 131: Irq Status Register (Irqr)
6.2.5 IRQ Status Register (IRQR) Bit : IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F — — Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * — — R/W : Note: * Only 0 can be written, to clear the flag. IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests.
Page 132: Port Mode Register (Pmr1)
6.2.6 Port Mode Register (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is specified for each bit. PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Only bits 5 to 0 are explained here.
Page 133: Interrupt Sources
Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts. 6.3.1 External Interrupts There are seven external interrupt sources; NMI and IRQ5 to IRQ0. Of these, NMI, and IRQ1 to IRQ0 can be used to restore this chip from standby mode. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode and the status of the CPU interrupt mask bits.
Page 134 Figure 6.3 shows the timing of IRQnF setting. Internal IRQn input pin IRQnF Figure 6.3 Timing of IRQnF Setting The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26. Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port mode register 1 (PMR1) as ,54Q pin.
Page 135: Internal Interrupts
6.3.2 Internal Interrupts There are 38 sources for internal interrupts from on-chip supporting modules. (1) For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller.
Page 136 Origin of Interrupt Vector Priority Interrupt Source Source Vector address Remarks  High Address trap H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F ICRA6 HSW1 Servo circuit H'0050 to H'0053 ICRA5 IRQ0 External pin H'0054 to H'0057 ICRA4 IRQ1 H'0058 to H'005B...
Page 137 Origin of Interrupt Vector Priority Interrupt Source Source Vector address Remarks High ICXA Timer X1 H'00B0 to H'00B3 ICRC7 ICXB H'00B4 to H'00B7 ICXC H'00B8 to H'00BB ICXD H'00BC to H'00BF OCX1 H'00C0 to H'00C3 OCX2 H'00C4 to H'00C7 OVFX H'00C8 to H'00CB VD interrupts Sync signal...
Page 138: Interrupt Operation
Interrupt Operation 6.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI interrupts and address trap interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 139 (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 6.6 shows the interrupts selected in each interrupt control mode. Table 6.6 Interrupts Selected in Each Interrupt Control Mode Interrupt...
Page 140: Interrupt Control Mode 0
6.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 141 Program execution state Interrupt generated? Address trap interrupt? Control level 1 Hold pending interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 Save PC and CCR Read vector address Branch to interrupt handling routine Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
Page 142: Interrupt Control Mode 1
6.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. (1) Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 143 (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending.
Page 144 Program execution state Interrupt generated? Address trap interrupt? Hold pending Control level 1 interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 I = 0 UI = 0 Save PC and CCR 1, UI Read vector address Branch to interrupt handling routine...
Page 145: Interrupt Exception Handling Sequence
6.4.4 Interrupt Exception Handling Sequence Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control 0 is set in advanced mode, and the program area and stack area are in on- chip memory. Figure 6.8 Interrupt Exception Handling Rev.
Page 146: Interrupt Response Times
6.4.5 Interrupt Response Times Table 6.8 shows interrupt response times-the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 6.8 are explained in table 6.9. Table 6.8 Interrupt Response Times Number of States Advanced Mode...
Page 147: Usage Notes
Usage Notes 6.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 148: Instructions That Disable Interrupts
6.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 149 Rev. 2.0, 11/00, page 122 of 1037...
Page 150: Section 7 Rom (H8S/2194 Series)
Section 7 ROM (H8S/2194 Series) Overview The H8S/2194 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2193 has 112 kbytes, the H8S/2192 has 96 kbytes, and the H8S/2191 has 80 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed.
Page 151: Overview Of Flash Memory
Overview of Flash Memory 7.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes — Program mode — Erase mode — Program-verify mode — Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units).
Page 152: Block Diagram
7.2.2 Block Diagram Internal address bus Internal data bus (16 bits) STCR FLMCR1 * Operat- FWE pin Bus interface/controller Mode pin FLMCR2 mode EBR1 EBR2 Flash memory (128 kbytes) [Legend] STCR : Serial timer control register FLMCR1 : Flash memory control register 1 FLMCR2 : Flash memory control register 2 EBR1...
Page 153: Flash Memory Operating Modes
7.2.3 Flash Memory Operating Modes (1) Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be read but not programmed or erased.
Page 154 (2) On-Board Programming Modes (a) Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the LSI (originally incorporated in the chip) is programming control program and new started and the programing control program in...
Page 155 (b) User program mode 1. Initial state 2. Programming/erase control program transfer When user program mode is entered, user software (1) The FWE assessment program that confirms that confirms this fact, executes the transfer program in the the FWE pin has been driven high, and (2) the flash memory, and transfers the programming/erase program that will transfer the programming/erase control program to RAM.
Page 156 (3) Differences between Boot Mode and User Program Mode Table 7.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: To be provided by the user, in accordance with the recommended algorithm. (4) Block Configuration The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Page 157: Pin Configuration
7.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 7.2. Table 7.2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 0 Input Sets this LSI operating mode Port 12...
Page 158: Flash Memory Register Descriptions
Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register 1 (FLMCR1) — — — * Initial value — — Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1.
Page 159 Bit 6: Software Write Enable (SWE) Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be cleared at the same time as these bits. Bit 6 Description Writes are disabled...
Page 160 Bit 1: Erase (E) Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 Description Erase mode cleared (Initial value) Transition to erase mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and ESU = 1 are selected Bit 0: Program (P) Selects program mode transition or clearing.
Page 161: Flash Memory Control Register 2 (Flmcr2)
7.3.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — Initial value — — — — — FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode.
Page 162 Bit 0: Program Setup (PSU) Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 0 Description Program setup cleared...
Page 163: Erase Block Registers 1 And 2 (Ebr1, Ebr2)
7.3.3 Erase Block Registers 1 and 2 (EBR1, EBR2) — — — — — — EBR1 Initial value — — — — — — EBR2 Initial value EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 0 in EBR1 (128-kbyte versions only) and bits 7 to 0 in EBR2 are readable/writable bits.
Page 164: Serial/Timer Control Register (Stcr)
7.3.4 Serial/Timer Control Register (STCR) — IICX IICRST — FLSHE — — — Initial value — — — — — STCR is an 8-bit readable/writable register that controls register access, the I C bus interface operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I C bus interface serial clock frequency.
Page 165: On-Board Programming Modes
On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 7.5.
Page 166: Boot Mode
7.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI1.
Page 167 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment...
Page 168 (1) Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 7.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Page 169 (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the 2048-byte area from H'FFEFB0 to H'FFF7AF is reserved for use by the boot program, as shown in figure 7.10. The area to which the programming control program is transferred is H'FFF7B0 to H'FFFF2F (1920 bytes). The boot program area can be used when the programming control program transferred into RAM enters the execution state.
Page 170 (3) Notes on Use of Boot Mode: (a) When reset is released in boot mode, it measures the low period of the input at the SCI1's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input.
Page 171: User Program Mode
7.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Page 172: Programming/Erasing Flash Memory
Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
Page 173: Program-Verify Mode
7.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later).
Page 174 Programming must be excuted in the erased state. START Do not perform additional programming on Set SWE bit in FLMCR1 addresses that have already been programmed. Wait (x) µs Store 32-byte program data in program data area and reprogram data area n = 1 m = 0 Write 32-byte data in RAM reprogram data...
Page 175: Erase Mode
7.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 7.13. Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, α, β, γ, ε and η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum clearing count (N).
Page 176 START Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms Halt erase Clear E bit in FLMCR1 Wait ( ) µs Clear ESU bit in FLMCR2 Wait ( ) µs...
Page 177: Flash Memory Protection
Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2).
Page 178: Software Protection
7.6.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode.
Page 179: Error Protection
7.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
Page 180: Interrupt Handling When Programming/Erasing Flash Memory
Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode , to give priority to the program or erase operation.
Page 181: Flash Memory Programmer Mode
Flash Memory Programmer Mode 7.8.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash memory.
Page 182: Programmer Mode Operation
7.8.3 Programmer Mode Operation Table 7.10 shows how the different operating modes are set when using programmer mode, and table 7.11 lists the commands used in programmer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time.
Page 183 Table 7.11 Programmer Mode Commands 1st Cycle 2nd Cycle Number of Command Name Cycles Mode Address Data Mode Address Data Memory read mode write H'00 read Dout Auto-program mode write H'40 write Auto-erase mode write H'20 write H'20 Status read mode write H'71 write...
Page 184: Memory Read Mode
7.8.4 Memory Read Mode (1) After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. (2) Command writes can be performed in memory read mode, just as in the command wait state.
Page 185 Table 7.13 AC Characteristics when Entering Another Mode from Memory Read Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Command write cycle nxtc &(  hold time &( ...
Page 186 Table 7.14 AC Characteristics in Memory Read Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Access time &(  output delay time  output delay time  Output disable delay time ...
Page 187: Auto-Program Mode
7.8.5 Auto-Program Mode (a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (c) The lower 8 bits of the transfer address must be H'00 or H'80.
Page 188 Table 7.15 AC Characteristics in Auto-Program = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Command write cycle nxtc &(  hold time &(  setup time  Data hold time ...
Page 189: Auto-Erase Mode
7.8.6 Auto-Erase Mode (a) Auto-erase mode supports only entire memory erasing. (b) Do not perform a command write during auto-erasing. (c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
Page 190: Status Read Mode
ADDRESS ests nxtc (100 to 40000ms) nxtc erase Erase end identification signal Erase normal end identification signal FO0 to 5 = 0 FO5 to FO0 H'20 H'20 Figure 7.21 Auto-Erase Mode Timing Waveforms 7.8.7 Status Read Mode (1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 191 ADDRESS nxtc nxtc nxtc H'71 H'71 DATA DATA Note: FO2 and FO3 are undefined. Figure 7.22 Status Read Mode Timing Waveforms Table 7.18 Status Read Mode Return Commands Pin Name   Attribute Normal Command Program- Erase Program- Effective error ming error error ming or...
Page 192: Status Polling
7.8.8 Status Polling (1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. (2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto- erase mode. Table 7.19 Status Polling Output Truth Table Internal Operation ...
Page 193: Programmer Mode Transition Time
7.8.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 7.20 Command Wait State Transition Time Specifications Item Symbol Unit...
Page 194: Flash Memory Programming And Erasing Precautions
Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and programmer mode are summarized below. (1) Use the Specified Voltages and Timing for Programming and Erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash memory.
Page 195 (5) Use the Recommended Algorithm when Programming and Erasing Flash Memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc.
Page 196: Note On Switching From F-Ztat Version To Mask Rom Version
7.10 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 7.21 lists the registers that are present in the F-ZTAT version but not in the mask ROM version.
Page 197 Rev. 2.0, 11/00, page 170 of 1037...
Page 198: Section 8 Rom (H8S/2194C Series)
Section 8 ROM (H8S/2194C Series) Overview The H8S/2194C has 256 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2194B has 192 kbytes, the H8S/2194A has 160 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed.
Page 199: Overview Of Flash Memory
Overview of Flash Memory 8.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes — Program mode — Erase mode — Program-verify mode — Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units).
Page 200: Block Diagram
8.2.2 Block Diagram Internal address bus Internal data bus (16 bits) STCR FLMCR1 * Operat- FWE pin Bus interface/controller Mode pin FLMCR2 mode EBR1 EBR2 Flash memory (256 kbytes) [Legend] STCR : Serial timer control register FLMCR1 : Flash memory control register 1 FLMCR2 : Flash memory control register 2 EBR1...
Page 201: Flash Memory Operating Modes
8.2.3 Flash Memory Operating Modes (1) Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 8.3. In user mode, flash memory can be read but not programmed or erased.
Page 202 (2) On-Board Programming Modes (a) Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the LSI (originally incorporated in the chip) is programming control program and new started and the programing control program in...
Page 203 (b) User program mode 1. Initial state 2. Programming/erase control program transfer When user program mode is entered, user software (1) The FWE assessment program that confirms that confirms this fact, executes the transfer program in the the FWE pin has been driven high, and (2) the flash memory, and transfers the programming/erase program that will transfer the programming/erase control program to RAM.
Page 204 (3) Differences between Boot Mode and User Program Mode Table 8.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: To be provided by the user, in accordance with the recommended algorithm. (4) Block Configuration The flash memory is divided into six 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Page 205: Pin Configuration
8.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 8.2. Table 8.2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 0 Input Sets this LSI operating mode Port 12...
Page 206: Flash Memory Register Descriptions
Flash Memory Register Descriptions 8.3.1 Flash Memory Control Register 1 (FLMCR1) ESU1 PSU1 — * Initial value Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE to 1 while FWE is 1 and then setting the EV1 bit or PV1 bit.
Page 207 Bit 6: Software Write Enable (SWE) Enables or disables flash memory programming. SWE should be set before setting bits 5 to 0, bits 5 to 0 in FLMCR2, bits 5 to 0 in EBR1 and bits 7 to 0 in EBR2. Bit 6 Description Writes are disabled...
Page 208 Bit 2: Program-Verify (PV1) Selects program-verify mode transition or clearing. Do not set the SWE, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected Bit 1: Erase (E1) Selects erase mode transition or clearing.
Page 209: Flash Memory Control Register 2 (Flmcr2)
8.3.2 Flash Memory Control Register 2 (FLMCR2) FLER — ESU2 PSU2 Initial value — FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'20000 to H'3FFFF is entered by setting SWE in FLMCR1 to 1 while FWE in FLMCR1 is 1 and then setting the EV2 bit or PV2 bit.
Page 210 Bit 5: Erase-Setup Bit 2 (ESU2) Prepares erase-mode transition for addresses H'20000 to H'3FFFF. Set ESU2 to 1 before setting the E2 bit to 1. Do not set the PSU2, EV2, PV2, E2, or P2 bit at the same time. Bit 5 ESU2 Description...
Page 211 Bit 1: Erase 2 (E2) Selects erase mode transition or clearing for addresses H'20000 to H'3FFFF. Do not set the ESU2, PSU2, EV2, PV2, or P2 bit at the same time. Bit 1 Description Erase mode cleared (Initial value) Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU2 = 1 Bit 0: Program 2 (P2) Selects program-mode transition or clearing for addresses H'20000 to H'3FFFF.
Page 212: Erase Block Registers 1 (Ebr1)
8.3.3 Erase Block Registers 1 (EBR1) EBR1 — — EB13 EB12 EB11 EB10 Initial value — — EBR1 is a register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set.
Page 213 Table 8.4 Flash Memory Erase Blocks Block (Size) 128-kbyte Versions Address EB0 (1 kbyte) H'000000 to H'0003FF EB1 (1 kbyte) H'000400 to H'0007FF EB2 (1 kbyte) H'000800 to H'000BFF EB3 (1 kbyte) H'000C00 to H'000FFF EB4 (28 kbytes) H'001000 to H'007FFF EB5 (16 kbytes) H'008000 to H'00BFFF EB6 (8 kbytes)
Page 214: Serial/Timer Control Register (Stcr)
8.3.5 Serial/Timer Control Register (STCR) — IICX IICRST — FLSHE — — — Initial value — — — — — STCR is an 8-bit readable/writable register that controls register access, the I C bus interface operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the I C bus interface serial clock frequency.
Page 215: On-Board Programming Modes
On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 8.5.
Page 216: Boot Mode
8.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI1.
Page 217 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment...
Page 218 (1) Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 8.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Page 219 (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the RAM area is divided into; the area for use by the boot program and the area to which programming control program is transferred by the SCI, as shown in figure 8.10.
Page 220 (3) Notes on Use of Boot Mode: (a) When reset is released in boot mode, it measures the low period of the input at the SCI1's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input.
Page 221: User Program Mode
8.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Page 222: Programming/Erasing Flash Memory
Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. For addresses H'00000 to H'1FFFF, transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in FLMCR1 and for addresses H'20000 to H'3FFFF, transitions to these modes can be made by setting the PSU2, ESU2, P2, E2, PV2 and EV1 bits in FLMCR2.
Page 223: Program-Verify Mode (N =1 For Addresses H'00000 To H'1Ffff And N = 2 For Addresses H'20000 To H'3Ffff)
program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) µs.
Page 224 Programming must be excuted in the erased state. START Do not perform additional programming on Set SWE bit in FLMCR1 addresses that have already been programmed. Wait (x) µs Store 32-byte program data in program data area and reprogram data area n = 1 m = 0 Write 32-byte data in RAM reprogram data...
Page 225: Erase Mode (N = 1 For Addresses H'00000 To H'1Ffff And N = 2 For Address H'20000 To H'3Ffff)
8.5.3 Erase Mode (n = 1 for addresses H'00000 to H'1FFFF and n = 2 for address H'20000 to H'3FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 8.13. Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, α, β, γ, ε...
Page 226 START Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 or FLMCR2 Wait (y) µs Start of erase Set E bit in FLMCR1 or FLMCR2 Wait (z) ms Halt erase Clear E bit in FLMCR1 or FLMCR2 Wait ( ) µs...
Page 227: Flash Memory Protection
Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 8.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2).
Page 228: Software Protection
8.6.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or setting the P2 or E2 bit in flash memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.
Page 229: Error Protection
8.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
Page 230: Interrupt Handling When Programming/Erasing Flash Memory
Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the Pn or En bit is set in FLMCRn), and while the boot program is executing in boot mode , to give priority to the program or erase operation.
Page 231: Flash Memory Programmer Mode
Flash Memory Programmer Mode 8.8.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash memory.
Page 232: Programmer Mode Operation
8.8.3 Programmer Mode Operation Table 8.10 shows how the different operating modes are set when using programmer mode, and table 8.11 lists the commands used in programmer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time.
Page 233 Table 8.11 Programmer Mode Commands 1st Cycle 2nd Cycle Number of Command Name Cycles Mode Address Data Mode Address Data Memory read mode write H'00 read Dout Auto-program mode write H'40 write Auto-erase mode write H'20 write H'20 Status read mode write H'71 write...
Page 234: Memory Read Mode
8.8.4 Memory Read Mode (1) After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. (2) Command writes can be performed in memory read mode, just as in the command wait state.
Page 235 Table 8.13 AC Characteristics when Entering Another Mode from Memory Read Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Command write cycle nxtc &(  hold time &( ...
Page 236 Table 8.14 AC Characteristics in Memory Read Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Access time &(  output delay time  output delay time  Output disable delay time ...
Page 237: Auto-Program Mode
8.8.5 Auto-Program Mode (a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (c) The lower 8 bits of the transfer address must be H'00 or H'80.
Page 238 Table 8.15 AC Characteristics in Auto-Program = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C) (Conditions: V Item Symbol Unit  µs Command write cycle nxtc &(  hold time &(  setup time  Data hold time ...
Page 239: Auto-Erase Mode
8.8.6 Auto-Erase Mode (a) Auto-erase mode supports only entire memory erasing. (b) Do not perform a command write during auto-erasing. (c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin).
Page 240: Status Read Mode
ADDRESS ests nxtc (100 to 40000ms) nxtc erase Erase end identification signal Erase normal end identification signal FO0 to 5 = 0 FO5 to FO0 H'20 H'20 Figure 8.21 Auto-Erase Mode Timing Waveforms 8.8.7 Status Read Mode (1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 241 ADDRESS nxtc nxtc nxtc H'71 H'71 DATA DATA Note: FO2 and FO3 are undefined. Figure 8.22 Status Read Mode Timing Waveforms Table 8.18 Status Read Mode Return Commands Pin Name   Attribute Normal Command Program- Erase Program- Effective error ming error error ming or...
Page 242: Status Polling
8.8.8 Status Polling (1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. (2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto- erase mode. Table 8.19 Status Polling Output Truth Table Internal Operation ...
Page 243: Programmer Mode Transition Time
8.8.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 8.20 Command Wait State Transition Time Specifications Item Symbol Unit...
Page 244: Flash Memory Programming And Erasing Precautions
Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and programmer mode are summarized below. (1) Use the Specified Voltages and Timing for Programming and Erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Hitachi microcomputer device type with 256-kbyte on-chip flash memory.
Page 245 (5) Use the Recommended Algorithm when Programming and Erasing Flash Memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the Pn or En bit in FLMCR1 and FLMCR2, the watchdog timer should be set beforehand as a precaution against program runaway, etc.
Page 246: Note On Switching From F-Ztat Version To Mask Rom Version
8.10 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 8.21 lists the registers that are present in the F-ZTAT version but not in the mask ROM version.
Page 247 Rev. 2.0, 11/00, page 220 of 1037...
Page 248: Section 9 Ram
Section 9 RAM Overview The H8S/2194C, H8S/2194B, and H8S/2194A have 6 kbytes, and the H8S/2194, H8S/2193, H8S/2192 and H8S/2191 have 3 kbytes, of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state.
Page 249 Rev. 2.0, 11/00, page 222 of 1037...
Page 250: Section 10 Clock Pulse Generator
Section 10 Clock Pulse Generator 10.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
Page 251: Register Descriptions
10.2 Register Descriptions 10.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Register (SBYCR).
Page 252: Low-Power Control Register (Lpwrcr)
10.2.2 Low-Power Control Register (LPWRCR) DTON LSON NESEL — — — Initial value — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, Low- Power Control Register (LPWRCR).
Page 253: Oscillator
10.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 10.3.1 Connecting a Crystal Resonator (1) Circuit Configuration A crystal resonator can be connected as shown in the example in figure 10.2. An AT-cut parallel-resonance crystal should be used.
Page 254 (3) Note on Board Design When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 10.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins.
Page 255: External Clock Input
10.3.2 External Clock Input (1) Circuit Configuration An external clock signal can be input as shown in the examples in figure 10.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode.
Page 256 (2) External Clock The external clock signal should have the same frequency as the system clock (φ). Table 10.3 and figure 10.6 show the input conditions for the external clock. Table 10.3 External Clock Input Conditions = 4.0 to 5.5 V Item Symbol Unit...
Page 257 Table 10.4 External Clock Output Settling Delay Time (Conditions: V = 4.0 V to 5.5 V, AV = 4.0 V to 5.5 V, V = AV = 0 V) Item Symbol Unit Notes  µs External clock output settling Figure 10.7 DEXT delay time Note:...
Page 258: Duty Adjustment Circuit
10.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 10.5 Medium-Speed Clock Divider The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks. 10.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed...
Page 259: Subclock Oscillator Circuit
10.7 Subclock Oscillator Circuit 10.7.1 Connecting 32.768 kHz Crystal Resonator When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in figure 10.8. For precautions on connecting, see section 10.3.1 (3), Note on Board Design. The subclock input conditions are shown in figure 10.10.
Page 260: External Clock Input
10.7.2 External Clock Input (1) Circuit Configuration When external clock input connect to the X1 pin, and X2 pin should remain open as connection example of figure 10.10. External clock input Open Figure 10.10 Connection Example When Inputting External Clock 10.7.3 When Subclock is not Needed Connect X1 pin to V...
Page 261: Subclock Waveform Shaping Circuit
10.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a clock obtained by dividing the φ clock. The sampling frequency is set with the NESEL bit in LPWRCR.
Page 262: Section 11 I/O Port
Section 11 I/O Port 11.1 Overview 11.1.1 Port Functions This LSI has seven 8-bit I/O ports (including one CMOS high-current port), one 4-bit I/O port, and one 8-bit input port. Table 11.1 shows the functions of each port. Each I/O part a port control register (PCR) that controls an input and output and a port data register (PDR) for storing output data.
Page 263 Table 11.1 Port Functions Function Switching Port Description Pins Alternative Functions Register Port 0 P07 to P00 input-only P70/AN7 to Analog data input channels 7 to 0 PMR0 ports P00/AN0 Port 1 P17 to P10 I/O ports P17/TMOW Prescalar unit frequency division clock PMR1 (Built-in MOS pull-up output...
Page 264: Mos Pull-Up Transistors
11.1.3 MOS Pull-Up Transistors The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin function is set to an input by PCR1 to PCR3.
Page 265: Port 0
11.2 Port 0 11.2.1 Overview Port 0 is an 8-bit input-only port. Table 11.2 shows the port 0 configuration. Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input channels (AN7 to AN0). It is switched by port mode register 0 (PMR0). Table 11.2 Port 0 Configuration Port Function...
Page 266: Register Configuration
11.2.2 Register Configuration Table 11.3 shows the port 0 register configuration. Table 11.3 Port 0 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 0 PMR0 Byte H'00 H'FFCD  Port data register 0 PDR0 Byte H'FFC0 Note: Lower 16 bits of the address.
Page 267: Pin Functions
(2) Port Data Register 0 (PDR0) Bit : PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 Initial value : — — — — — — — — R/W : Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0 (general input port), the pin state is read if PDR0 is read.
Page 268: Port 1
11.3 Port 1 11.3.1 Overview Port 1 is an 8-bit I/O port. Table 11.5 shows the port 1 configuration. Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division clock output (TMOW), input capture input ( ,& ), or external interrupt request inputs ( ,54 to ,54 ).
Page 269 (1) Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
Page 270 Bit 6: P16/ ,& ,& Pin Switching (PMR16) PMR16 sets whether the P16/ ,& pin as a P16 I/O pin or an ,& pin for the input capture input of the prescalar unit. The ,& pin has a built-in noise cancel circuit. See section 21, Prescalar Unit. Bit 6 PMR16 Description...
Page 271 (3) Port Data Register 1 (PDR1) Bit : PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 Initial value : R/W : Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1 (output), the PDR1 values are directly read if port 1 is read.
Page 272: Pin Functions
11.3.3 Pin Functions This section describes the port 1 pin functions and their selection methods. (1) P17/TMOW P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the PCR17 bit in PCR1. PMR17 PCR17 Pin Function P17 input pin P17 output pin TMOW output pin...
Page 273: Pin States
11.3.4 Pin States Table 11.7 shows the port 1 pin states in each operation mode. Table 11.7 Port 1 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P17/TMOW High- Operation Holding High- High- Operation Holding ,& P16/ impedance impedance impedance ,54...
Page 274: Port 2
11.4 Port 2 11.4.1 Overview Port 2 is an 8-bit I/O port. Table 11.8 shows the port 2 configuration. Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O (SCK1, SCK2), receive data input (SI1, SI2), send data output (SO1, SO2), I C bus interface clock I/O (SCL), or data I/O (SCL).
Page 275 (1) Port Mode Register 2 (PMR2) Bit : PMR27 PMR26 PMR25 — — — — PMR20 Initial value : — — — — R/W : Port mode register 2 (PMR0) controls switching of each pin function of port 2. The switching is specified in a unit of bit.
Page 276 Bit 5: P25/SI2 Pin Switching (PMR25) PMR26 sets whether the P25/SI2 pin as a P25 I/O pin or an SI2 pin for the SCI2 receive data input. Bit 5 PMR25 Description The P25/SI2 pin functions as a P25 I/O pin (Initial value) The P25/SI2 pin functions as an SI2 input pin Bits 4 to 1: Reserved Bits...
Page 277 (3) Port Data Register 2 (PDR2) Bit : PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 Initial value : R/W : Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1 (output), the PDR2 values are directly read if port 2 is read.
Page 278: Pin Functions
11.4.3 Pin Functions This section describes the port 2 pin functions and their selection methods. (1) P27/SCK2 P27/SCK2 is switched as shown below according to the PMR27 bit in PMR2, the PCR27 bit in PCR2, and the SCK2 to SCK0 bits in serial control register 2 (SCR2). PMR27 PCR27 CKS2 to CKS0...
Page 279 (4) P24/SCL P24/SCL2 is switched as shown below according to the ICE bit in the I C bus control register and the PCR24 bit in PCR2. PCR24 Pin Function P24 input pin P24 output pin SCL I/O pin Note: Don't care. (5) P23/SDA P23/SDA is switched as shown below according to the ICE bit in the I C bus control register...
Page 280: Pin States
PCR21 Pin Function P21 input pin P21 output pin SO1 output pin Note: Don't care. (8) P20/SI1 P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit in SCR. PCR20 Pin Function P20 input pin P20 output pin SI1 input pin Note:...
Page 281: Port 3
11.5 Port 3 11.5.1 Overview Port 3 is an 8-bit I/O port. Table 11.11 shows the port 3 configuration. Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer output (TMO), buzzer output (BUZZ), 8-bit PWN outputs (PWN3 to PWN0), SCI2 strobe output (STRB), or chip select input ( ).
Page 282 (1) Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is specified in a unit of bit. PMR3 is an 8-bit read/write enable register.
Page 283 Bits 5 to 2: P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32) PMR35 to PMR32 set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM output. Bit n PMR3n Description The P3n/PWMm pin functions as a P3n I/O pin (Initial value) The P3n/PWMm pin functions as a PWMm output pin...
Page 284 (2) Port Control Register 3 (PCR3) Bit : PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 Initial value : R/W : Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit. When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set to 0, they become input pins.
Page 285: Pin Functions
(4) MOS Pull-Up Select Register 3 (PUR3) Bit : PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30 Initial value : R/W : MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and the MOS pull-up transistor is turned off.
Page 286 (2) P36/BUZZ P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36 bit in PCR3. PMR36 PCR36 Pin Function P36 input pin P36 output pin BUZZ output pin Note: Don't care. (3) P35/PWM3 to P32/PWM0 P35/PWM3 to P32/PWM0 are switched as shown below according to the PMR3n bit in PMR3 and the PCR3n bit in PCR3.
Page 287: Pin States
11.5.4 Pin States Table 11.13 shows the port 3 pin states in each operation mode. Table 11.13 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P37/TMO High- Operation Holding High- High- Operation Holding P36/BUZZ impedance impedance impedance P35/PWM3 P32/PWM0...
Page 288: Port 4
11.6 Port 4 11.6.1 Overview Port 4 is an 8-bit I/O port. Table 11.14 shows the port 4 configuration. Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output (PWM14).
Page 289 (1) Port Mode Register 4 (PMR4) Bit : — — — — — — — PMR40 Initial value : R/W : — — — — — — — Port mode register 4 (PMR4) controls switching of the P40/PWM14 pin function. The switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR.
Page 290 (2) Port Control Register 4 (PCR4) Bit : PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40 Initial value : R/W : Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit. When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set to 0, they become input pins.
Page 291: Pin Functions
11.6.3 Pin Functions This section describes the port 4 pin functions and their selection methods. (1) P47/FTCI P47/FTCI is switched as shown below according to the PCR47 bit in PCR4. PCR47 Pin Function P47 input pin P47 output pin (2) P46/FTOB P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the OEB bit in TOCR.
Page 292 (5) P43/FTIC P43/FTIC is switched as shown below according to the PCR43 bit in PCR4. PCR43 Pin Function P43 input pin FTIC input pin P43 output pin (6) P42/FTIB P42/FTIB is switched as shown below according to the PCR42 bit in PCR4. PCR42 Pin Function P42 input pin...
Page 293: Pin States
11.6.4 Pin States Table 11.16 shows the port 4 pin states in each operation mode. Table 11.16 Port 4 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep High- Operation Holding High- High- Operation Holding P46/FTOB impedance impedance impedance P45/FTOA P44/FTID P43/FTIC...
Page 294: Port 5
11.7 Port 5 11.7.1 Overview Port 5 is a 4-bit I/O port. Table 11.17 shows the port 5 configuration. Port 5 consists of pins that are used both as standard I/O ports (P53 to P50) and realtime output port trigger input (TRIG), timer B event input (TMBI), or A/D conversion start external trigger '75* input ( ).
Page 295 (1) Port Mode Register 5 (PMR5) Bit : PMR53 PMR52 PMR51 — — — — — Initial value : R/W : — — — — — Port mode register 5 (PMR5) controls switching of each pin function of port 5 and specifies the edge sense of the timer B event input (TMBI).
Page 296 Bit 1: Timer B event input edge select (PMR51) PMR51 selects the input edge sense of the TMBI pin. Bit 1 PMR51 Description The timer B event input detects the falling edge (Initial value) The timer B event input detects the rising edge Bit 0: Reserved Bit When the bit is read, 1 is always read.
Page 297 (3) Port Data Register 5 (PDR5) Bit : — — — — PDR53 PDR52 PDR51 PDR50 Initial value : R/W : — — — — Port data register 5 (PDR5) stores the data for the pins P53 to P50 of port 5. When PCR5 is 1 (output), the PDR5 values are directly read if port 5 is read.
Page 298: Pin Functions
11.7.3 Pin Functions This section describes the port 5 pin functions and their selection methods. (1) P53/TRIG P53/TRIG is switched as shown below according to the PMR53 bit in PMR5 and the PCR53 bit in PCR5. PMR53 PCR53 Pin Function P53 input pin P53 output pin TRIG input pin...
Page 299: Pin States
11.7.4 Pin States Table 11.19 shows the port 5 pin states in each operation mode. Table 11.19 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P53/TRIG High- Operation Holding High- High- Operation Holding P52/TMBI impedance impedance impedance P50/ $'57*...
Page 300: Port 6
11.8 Port 6 11.8.1 Overview Port 6 is an 8-bit I/O port. Table 11.20 shows the port 6 configuration. Port 6 consists of pins that are used both as standard I/O ports (P67 to P60) and realtime output ports (RP7 to RP0). It is switched by port mode register 6 (PMR6) and port control register 6 (PCR6).
Page 301: Register Configuration
11.8.2 Register Configuration Table 11.21 shows the port 6 register configuration. Table 11.21 Port 6 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 6 PMR6 Byte H'00 H'FFDD Port control register 6 PCR6 Byte H'00 H'FFD6 Port data register 6 PDR6 Byte H'00...
Page 302 (2) Port Control Register 6 (PCR6) Bit : PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial value : R/W : Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in a unit of bit together with PMR6. When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to 1, and they become general input pins if it is set to 0.
Page 303 (4) Realtime Output Trigger Select Register (RTPSR) Bit : RTPSR7 RTPSR6 RTPSR5 RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0 Initial value : R/W : The realtime output trigger select register (RTPSR) sets whether the external trigger (TRIG pin input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of bit.
Page 304: Pin Functions
(5) Real Time Output Trigger Edge Select Register (RTPEGR) Bit : — — — — — — RTPEGR1 RTPEGR0 Initial value : R/W : — — — — — — The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external or internal trigger input for the realtime output.
Page 305: Operation
11.8.4 Operation Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation per port 6 function is shown below.
Page 306: Pin States
(1) Operation of the Realtime Output Port (PMR6 = 1) When PMR6 is 1, it operates as a realtime output port. When a trigger is input, PMR6 transfers the PDR6 data to PDRS6 and the PCR6 data to PCRS6, respectively. In this case, when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin.
Page 307: Port 7
11.9 Port 7 11.9.1 Overview Port 7 is an 8-bit I/O port. Table 11.23 shows the port 7 configuration. Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched by port mode register 7 (PMR7) and port control register 7 (PCR7).
Page 308 (1) Port Mode Register 7 (PMR7) Bit : PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70 Initial value : R/W : Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is specified in a unit of bit. PMR7 is an 8-bit read/write enable register.
Page 309: Pin Functions
(3) Port Data Register 7 (PDR7) Bit : PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70 Initial value : R/W : Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7. When PCR7 is 1 (output), the PDR7 values are directly read if port 7 is read. Accordingly, the pin states are not affected.
Page 310: Port 8
11.10 Port 8 11.10.1 Overview Port 8 is an 8-bit I/O port. Table 11.26 shows the port 8 configuration. Port 8 is a CMOS high-current I/O port. The sink current is 20 mA max. (V = 1.5 V) and up to four pins can simultaneously be set on.
Page 311 (1) Port Mode Register 8 (PMR8) Bit : — — — — PMR83 PMR82 PMR81 PMR80 Initial value : R/W : — — — — Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is specified in a unit of bit.
Page 312 Bit 1: P81/EXCAP Pin Switching (PMR81) PMR81 sets whether the P83/EXCAP pin is used as a P81 I/O pin or an EXTTRG pin for the capstan external synchronous signal input. Bit 1 PMR81 Description The P81/EXCAP pin functions as a P81 I/O pin (Initial value) The P81/EXCAP pin functions as an EXCAP input pin Bit 0: P80/EXTTRG Pin Switching (PMR80)
Page 313: 11.10.3 Pin Functions
(3) Port Data Register 8 (PDR8) Bit : PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80 Initial value : R/W : Port data register 8 (PDR8) stores the data for the pins P87 to P80 of port 8. When PCR8 is 1 (output), the PDR8 values are directly read if port 8 is read. Accordingly, the pin states are not affected.
Page 314 (3) P82/SV1 P82/SV1 is switched as shown below according to the PMR82 bit in PRM8 and the PCR82 bit in PCR8. PMR82 PCR82 Pin Function P82 input pin P82 output pin SV1 output pin Note: Don't care. (4) P81/EXCAP P81/EXCAP is switched as shown below according to the PMR81 bit in PRM8 and the PCR81 bit in PCR8.
Page 315: 11.10.4 Pin States
11.10.4 Pin States Table 11.28 shows the port 8 pin states in each operation mode. Table 11.28 Port 8 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P87 to P84 High- Operation Holding High- High- Operation Holding P83/SV2 impedance impedance impedance...
Page 316: Section 12 Timer A
Section 12 Timer A 12.1 Overview The Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 12.1.1 Features Features of the Timer A are as follows: •...
Page 317: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the Timer A. 32 kHz Prescaler W Crystal oscillator (PSW) w/128 Overflowing of the interval /16384, /8192, timer /4096, /1024, /512, /256, /64, /16 Prescaler S System Interrupting (PSS) clock Interrupt circuit requests...
Page 318: Descriptions Of Respective Registers
12.2 Descriptions of Respective Registers 12.2.1 Timer Mode Register A (TMA) Bit : TMAOV TMAIE — — TMA3 TMA2 TMA1 TMA0 Initial value : R/(W) * — — R/W : Note: * Only 0 can be written to clear the flag. The timer mode register A (TMA) works to control the interrupts of the Timer A and to select the input clock.
Page 319 Bit 3: Selection of the Clock Source and Prescaler (TMA3) This bit works to select the PSS or PSW as the clock source for the Timer A. Bit 3 TMA3 Description Selects the PSS as the clock source for the Timer A (Initial value) Selects the PSW as the clock source for the Timer A Bits 2 to 0: Clock Selection (TMA2 to TMA0)
Page 320: Timer Counter A (Tca)
12.2.2 Timer Counter A (TCA) Bit : TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value : R/W : The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA When the TCA overflows, the TMAOV bit of the TMA is set to 1.
Page 321: Operation
12.3 Operation The Timer A is an 8-bit timer for use as an interval timer and as a clock time base connecting to a 32.768 kHz crystal oscillator. 12.3.1 Operation as the Interval Timer When the TMA3 bit of the TMA is cleared to 0, the Timer A works as an 8-bit interval timer. When resetince the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues counting up as the interval counter without interrupts right after resetting.
Page 322: Section 13 Timer B
Section 13 Timer B 13.1 Overview The Timer B is an 8-bit up-counter. The Timer B is equipped with two different types of functions namely, the interval function and the auto reloading function. 13.1.1 Features • Selection from choices of seven different types of internal clocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32 and φ/8) or selection of external clock are possible.
Page 323: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the pin configuration of the Timer B. Table 13.1 Pin Configuration Name Abbrev. Function Event inputs to the Timer B TMBI Input Event input pin for inputs to the TCB 13.1.4 Register Configuration Table 13.2 shows the register configuration of the Timer B. The TCB and TLB are being allocated to the same address.
Page 324: Descriptions Of Respective Registers
13.2 Descriptions of Respective Registers 13.2.1 Timer Mode Register B (TMB) Bit : TMB17 TMBIF TMBIE — — TMB12 TMB11 TMB10 Initial value : R/(W) * R/W : — — Note: Only 0 can be written to clear the flag. The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock.
Page 325 Bit 5: Enabling Interrupt of the Timer B (TMBIE) This bit works to permit/prohibit occurrence of interrupt of the Timer B when the TCB overflows and when the TMBIF is set to 1. Bit 5 TMBIE Description Prohibits occurrence of interrupt of the Timer B (Initial value) Permits occurrence of interrupt of the Timer B Bits 4 to 3: Reserved...
Page 326: Timer Counter B (Tcb)
13.2.2 Timer Counter B (TCB) Bit : TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value : R/W : The TCB is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB. When the TCB overflows (H'FF →...
Page 327: Port Mode Register 5 (Pmr5)
13.2.4 Port Mode Register 5 (PMR5) Bit : PMR53 PMR52 PMR51 — — — — — Initial value : — — — — — R/W : The port mode register 5 (PMR5) works to changeover the pin functions of the port 5 and to designate the edge sense of the event inputs of the Timer B (TMBI).
Page 328 Bit 6: Module Stop (MSTP14) This bit works to designate the module stop mode for the Timer B. MSTPCRH Bit 6 MSTP14 Description Cancels the module stop mode of the Timer B Sets the module stop mode of the Timer B (Initial value) Rev.
Page 329: Operation
13.3 Operation 13.3.1 Operation as the Interval Timer When the TMB17 bit of the TMB is set to 0, the Timer B works as an 8-bit interval timer. When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, the Timer B continues counting up as the interval timer without interrupts right after resetting.
Page 330: Section 14 Timer J
Section 14 Timer J 14.1 Overview The Timer J consists of twin 8-bit counters. It carries seven different operation modes such as reloading and event counting. 14.1.1 Features The Timer J consists of twin 8-bit reloading timers and it is usable under the various functions as follows: (a) Twin 8-bit reloading timers (Among the two, one is capable to make timer outputs) (b) Twin 8-bit event counters (Capable to make reloading)
Page 331 BUZZ REMOout Toggle Edge detection Toggle 8/16 Reloading register Synchronization PS11,10 Figure 14.1 Block Diagram of the Timer J Rev. 2.0, 11/00, page 304 of 1037...
Page 332: Pin Configuration
14.1.3 Pin Configuration Table 14.1 shows the pin configuration of the Timer J. Table 14.1 Pin Configuration Name Abbrev. Function ,54 Event input pin Input Event inputs to the TMJ-1 ,54 Event input pin Input Event inputs to the TMJ-2 14.1.4 Register Configuration Table 14.2 shows the register configuration of the Timer J.
Page 333: Descriptions Of Respective Registers
14.2 Descriptions of Respective Registers 14.2.1 Timer Mode Register J (TMJ) Bit : PS11 PS10 8/16 PS21 PS20 Initial value : R/W : The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and to set the operation mode.
Page 334 Bit 5: Starting the Remote Controlled Operation (ST) This bit works to start the remote controlled operations. When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions. When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be valid under the remote controlling mode, namely, when the Bit 0 (T/R bit) is 1 and the Bit 4 (8/16 bit) is 0.
Page 335 Bits 3 and 2: Selecting the Inputting Clock to the TMJ-2 (PS21 and PS20) This bit works to select the clock to input to the TMJ-2. Selection of the leading edge or the trailing edge is workable for counting by use of an external clock. TMJC:Bit0 Bit 3 Bit 2...
Page 336 Selecting the Operation Mode The operation mode of the Timer J is determined by the Bit 4 (8/16) and Bit 0 (T/R) of the TMJ. Bit 4 Bit 0 8/16 Description 8-bit timer × 2 (Initial value) Remote controlling mode 16-bit timer Note: Don't care.
Page 337: Timer J Control Register (Tmjc)
14.2.2 Timer J Control Register (TMJC) Bit : (PS22) * — BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE Initial value : (R/W) * — R/W : Note: * Bit 0 is readable/writable only in the H8S/2194C series. The timer J control register works to select the buzzer output frequency and to control permission/prohibition of interrupts.
Page 338 Bits 5 and 4: Selecting the Monitor Signals (MON1 or MON0) These bits work to select the type of signals being output through the BUZZ pin for monitoring purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 1 and When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
Page 339: Timer J Status Register (Tmjs)
Bit 0: Reserved (for H8S/2194 series) When this is read, 1 will always be readout. Writes are disabled. Bit 0: Selecting the Input clock for TMJ-2 (PS22) (for H8S/2194C series) This bit, together with bits 3 and 2 (PS21, PS20) in TMJ, selects the input clock for TMJ-2. For details, see section 14.2.1, Timer Mode Register J (TMJ).
Page 340: Timer Counter J (Tcj)
14.2.4 Timer Counter J (TCJ) Bit : TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 Initial value : R/W : The time counter J (TCJ) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and PS10 bits of the TMJ.
Page 341: Timer Load Register J (Tlj)
14.2.6 Timer Load Register J (TLJ) Bit : TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 Initial value : R/W : The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading value of the TCJ. When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and the TCJ starts counting down from the set value.
Page 342: Module Stop Control Register (Mstpcr)
14.2.8 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP13 bit is set to 1, the Timer J stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 343: Operation
14.3 Operation 14.3.1 8-bit Reload Timer (TMJ-1) The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the ,54 pin are being used. By selecting the edge signals through the ,54 pin, it can also be used as an event counter.
Page 344: Remote Controlled Data Transmission
Regarding the remote controlled data transmission, see section 14.3.3, Remote Controlled Data Transmission. 14.3.3 Remote Controlled Data Transmission The Timer J is capable of making remote controlled data transmission. The carrier frequencies for the remote controlled data transmission can be generated by the TMJ-1 and the burst width duration and the space width duration can be setup by the TMJ-2.
Page 345 Figure 14.3 Timer Output Timing Rev. 2.0, 11/00, page 318 of 1037...
Page 346 When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote controlled data transmission starts.
Page 347 Rev. 2.0, 11/00, page 320 of 1037...
Page 348: Section 15 Timer L
Section 15 Timer L 15.1 Overview The Timer L is an 8-bit up/down counter using the control pulses or the CFG division signals as the clock source. 15.1.1 Features Features of the Timer L are as follows: • Choices of two different types of internal clocks (φ/128 and φ/64), DVCFG2 (CFG division signal 2), PB and REC-CTL (control pulses) are available for your selection.
Page 349: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the Timer L. INTERNAL CLOCK /128 Read DVCFG2 OVF/UDF PB and REC-CTL Reloading Match clear Comparator Interrupting circuit Write [Legend] DVCFG2 : Division signal 2 of the CFG Interrupt request PB and REC-CTL : Control pluses necessary when making reproduction and storage LMR : Timer L mode register...
Page 350: Register Configuration
15.1.3 Register Configuration Table 15.1 shows the register configuration of the Timer L. The linear time counter (LTC) and the reload compare patch register (RCR) are being allocated to the same address. Reading or writing determines the accessing register. Table 15.1 Register Configuration Name Abbrev.
Page 351: Descriptions Of Respective Registers
15.2 Descriptions of Respective Registers 15.2.1 Timer L Mode Register (LMR) Bit : LMIF LMIE IMR3 IMR2 IMR1 IMR0 — — Initial value : R /(W) * — — R/W : Note: * Only 0 can be written to clear the flag. The timer L mode register (LMR) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source.
Page 352 (1) When Controlled to the Up-counting Function • When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00 before starting counting up. When the LTC value and the RCR value match, the LTC will be cleared to H'00.
Page 353: Linear Time Counter (Ltc)
15.2.2 Linear Time Counter (LTC) Bit : LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : R/W : The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be selected by the LMR2 to LMR0 bits of the LMR. When reset, the LTC is initialized to H'00.
Page 354: Module Stop Control Register (Mstpcr)
15.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP12 bit is set to 1, the Timer L stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 355: Operation
15.3 Operation The Timer L is an 8-bit up/down counter. The inputting clock for the Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL. The Timer L is provided with three different types of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode.
Page 356 PB-CTL Count-up signal Compare match clear signal H' 00 Interrupt request Figure 15.3 Compare Match Clearing Timing Chart (In case the rising edge of the PB-CTL is selected) Rev. 2.0, 11/00, page 329 of 1037...
Page 357 Rev. 2.0, 11/00, page 330 of 1037...
Page 358: Section 16 Timer R
Section 16 Timer R 16.1 Overview The Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and slow tracking function in addition to the reloading function and event counter function. 16.1.1 Features The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: (1) Applications making use of the functions of three units of reloading timers.
Page 359 Figure 16.1 Block Diagram of the Timer R Rev. 2.0, 11/00, page 332 of 1037...
Page 360: Pin Configuration
16.1.3 Pin Configuration Table 16.1 shows the pin configuration of the Timer R. Table 16.1 Pin Configuration Name Abbrev. Function ,54 Input capture inputting pin Input Input capture inputting for the Timer R 16.1.4 Register Configuration Table 16.2 shows the register configuration of the Timer R. Table 16.2 Register Configuration Name Abbrev.
Page 361: Descriptions Of Respective Registers
16.2 Descriptions of Respective Registers 16.2.1 Timer R Mode Register 1 (TMRM1) Bit : CLR2 AC/BR RLCK PS21 PS20 RLD/CAP Initial value : R/W : The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes and to select the inputting clock for the TMRU-2.
Page 362 Bit 5: Selection if Using the TMRU-2 for Reloading or Not Doing So (RLD) This bit is used for selecting if the TMRU-2 reload function is to be turned on or not. Bit 5 Description Not using the TMRU-2 as the reload timer (Initial value) Using the TMRU-2 as the reload timer Bit 4: Selection of the Reloading Timing for the TMRU-2 (RLCK)
Page 363: Timer R Mode Register 2 (Tmrm2)
Bit 0: Selection of the Capture Signals of the TMRU-1 (CPS) In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set to 1.
Page 364 Bit 7: Selection of the Capture Signals of the TMRU-2 (LAT) In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture signals of the TMRU-2. TMRM2 TMRM1 Bit 7 Bit 0 Description Captures when the TMRU-3 underflows (Initial value) Captures at the rising edge of the CFS...
Page 365 Bit 2: Selection of Interrupt Causes (CP/SLM) This bit works to select the interrupt causes for the TMRI3. Bit 2 CP/SLM Description Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value) Makes interrupt requests upon ending of the slow tracking mono-multi valid Bit 1: Capture Signal Flag (CAPF) This is a flag being set out by the capture signal of the TMRU-2.
Page 366: Timer R Control/Status Register (Tmrcs)
16.2.3 Timer R Control/Status Register (TMRCS) Bit : — — TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 Initial value : R/(W) * R/(W) * R/(W) * — — R/W : Note: * Only 0 can be written to clear the flag. The timer R control/status register (TMRCS) works to control the interrupts of the Timer R.
Page 367 Bit 5: Enabling the TMRI1 Interrupt (TMRI1E) This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of the TMRU-1. Bit 5 TMRI1E Description Prohibits occurrences of TMRI1 interrupts (Initial value) Permits occurrences of TMRI1 interrupts Bit 4: TMRI3 Interrupt Requesting Flag (TMRI3)
Page 368: Timer R Capture Register 1 (Tmrcp1)
Bit 2: TMRI1 Interrupt Requesting Flag (TMRI1) This is the TMRI1 interrupt requesting flag. It indicates occurrences of the TMRU-1 underflow signals. Bit 2 TMRI1 Description [Clearing conditions] (Initial value) When 0 is written after reading 1. [Setting conditions] When the TMRU-1 underflows. Bits 1 and 0: Reserved When they are read, 1 will always be readout.
Page 369: Timer R Capture Register 2 (Tmrcp2)
16.2.5 Timer R Capture Register 2 (TMRCP2) Bit : TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : R/W : The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter readings are captured by the TMRCP2.
Page 370: Timer R Load Register 2 (Tmrl2)
16.2.7 Timer R Load Register 2 (TMRL2) Bit : TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 Initial value : R/W : The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load value of the TMRU-2.
Page 371: Module Stop Control Register (Mstpcr)
16.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP11 bit is set to 1, the Timer R stops its operation at the ending point of the bus cycle to shift to the module stop mode.
Page 372: Operation
16.3 Operation 16.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 The reload timer counter equipped with capturing function, TMRU-1, consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the leading edge of the CFG signals and three types of dividing clocks.
Page 373: Reload Timer Counter Equipped With Capturing Function Tmru-2
16.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 The reload timer counter equipped with capturing function, TMRU-2, consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three types of dividing clocks.
Page 374: Mode Identification
searches. These DVCTL signals can also be used for phase controls of the capstan motor. Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the DVCTL to provide the slow tracking mono-multi function. 16.3.4 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing...
Page 375: Slow Tracking Mono-Multi Function
(4) In case the acceleration has not been finished (in case the CFG signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), such underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be cleared by the CFG.
Page 376 Compensation for vertical vibrations (Supplementary V-pulse) FG acceleration detection Accelerating the Hi-Z capstan motor Acceleration process DVCTL Interrupt Slow tracking moto-multi Slow tracking delay FG stopping detection Reloading Reverse Braking the rotation capstan motor Forward rotation Braking process Braking the Servo drum motor Compensation for...
Page 377: Interrupt Cause
16.4 Interrupt Cause The interrupt causes for the Timer R are 3-causes of the TMRI3 bit through TMRI1 bit of the timer R control/status register (TMRCS). (a) Interrupts being caused by the underflowing of the TMRU-1 (TMRI1) These interrupts will constitute the timing for reloading with the TMRU-1. (b) Interrupts being caused by the underflowing of the TMRU-2 or by an end of the acceleration or braking process (TMRI2) When interrupts occur at the reload timing of the TMRU-2, clear the AC/BR...
Page 378: Exemplary Settings For Respective Functions
16.5 Exemplary Settings for Respective Functions 16.5.1 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used. The Timer R will become to the aforementioned status after a reset.
Page 379: Reeling Controls
16.5.2 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the ,54 pin, reeling controls, etc. can be effected. •...
Page 380: Acceleration And Braking Processes Of The Capstan Motor
(2) Setting the timer R load register 3 (TMRL3) Set the slow tracking delay value. When the delay count is "n", the set value should be (n - 1). Regarding the delaying duration, see figure 16.2 Exemplary time series movements when a slow reproduction is being performed.
Page 381 (2) Setting the timer R load register 2 (TMRL2) Set the count reading for the duration until the braking process finishes. When the count is "n", the set value should be (n - 1). Regarding the duration until the braking process finishes, see figure 16.2 Exemplary time series movements when a slow reproduction is being performed.
Page 382: Section 17 Timer X1
Section 17 Timer X1 17.1 Overview The Timer X1 is capable of outputting two different types of independent waveforms using the free running counter (FRC) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 17.1.1 Features Listed below are the features of the Timer X1.
Page 383: Block Diagram
17.1.2 Block Diagram Figure 17.1 shows a block diagram of the Timer X1. FTIA* ICRA (HSW) FTIB* (VD) ICRB Input FTIC* capture (DVCTL) control ICRC FTID* (NHSW) ICRD TCRX OCRB Comparison circuit (DVCFG) Comparison circuit / 16 / 64 OCRA Output comparing output FTOA TOCR...
Page 384: Pin Configuration
17.1.3 Pin Configuration Table 17.1 shows the pin configuration of the Timer X1. Table 17.1 Pin Configuration Name Abbrev. Function Output comparing A output-pin FTOA Output Output pin for the output comparing A Output comparing B output-pin FTOB Output Output pin for the output comparing B Input capture A input-pin FTIA Input...
Page 385: Register Configuration
17.1.4 Register Configuration Table 17.2 shows the register configuration of the Timer X1. Table 17.2 Register Configuration Name Abbrev. Initial Value Address Timer interrupt enabling register TIER H'00 H'D100 Timer control/status register X TCSRX R/ (W) H'00 H'D101 Free running counter H FRCH H'00 H'D102...
Page 386: Descriptions Of Respective Registers
17.2 Descriptions of Respective Registers 17.2.1 Free Running Counter (FRC) Free running counter H (FRCH) Free running counter L (FRCL) Bit : Initial value : R/W : FRCH FRCL The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock.
Page 387: Output Comparing Register A And B (Ocra And Ocrb)
17.2.2 Output Comparing Register A and B (OCRA and OCRB) Output comparing register AH and BH (OCRAH and OCRBH) Output comparing register AL and BL (OCRAL and OCRBL) OCRA, OCRB Bit : Initial value : R/W : OCRAH, OCRBH OCRAL, OCRBL The OCR consists of twin 8-bit read/write registers (OCRA and OCRB).
Page 388: Input Capture Register A Through D (Icra Through Icrd)
17.2.3 Input Capture Register A Through D (ICRA Through ICRD) Input capture register AH to DH (ICRAH to ICRDH) Input capture register AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit : Initial value : R/W : ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL The ICR consists of four 16-bit read only registers (ICRA through ICRD).
Page 389 IEDGA BUFEA IEDGC Edge detection and FTIA capture signal generating circuit. ICRC ICRA Figure 17.2 Buffer Operation (an example) Table 17.3 Input Signal Edge Selection when Making Buffer Operation IEDGA IEDGC Selection of the Input Signal Edge Captures at the rising edge of the input capture input A (Initial value) Captures at both rising and falling edges of the input capture input A Captures at the rising edge of the input capture input A Reading can be made from the ICR through the CPU at 8-bit or 16-bit.
Page 390: Timer Interrupt Enabling Register (Tier)
17.2.4 Timer Interrupt Enabling Register (TIER) Bit : ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Initial value : R/W : The TIER is an 8-bit read/write register which works to control permission/prohibition of respective interrupt requests. The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Page 391 Bit 4: Enabling the Input Capture Interrupt D (ICIDE) This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1. Bit 4 ICIDE Description Prohibits interrupt requests (ICID) by the ICFD (Initial value) Permits interrupt requests (ICID) by the ICFD Bit 3: Enabling the Output Comparing Interrupt A (OCIAE)
Page 392 Bit 0: Selecting the Input Capture A Signals (ICSA) This bit works to select the input capture A signals. Bit 0 ICSA Description Selects the FTIA pin for inputting of the input capture A signals (Initial value) Selects the HSW for inputting of the input capture A signals Rev.
Page 393: Timer Control/Status Register X (Tcsrx)
17.2.5 Timer Control/Status Register X (TCSRX) Bit : ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W : Note: * Only 0 can be written to clear the flag for Bits 7 to 1. The TCSRX is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals.
Page 394 Bit 6: Input Capture Flag B (ICFB) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRB by the input capture signals. When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value has been transferred to the ICRB by the input capture signals and that the ICRB value before being updated has been transferred to the ICRC.
Page 395 Bit 4: Input Capture Flag D (ICFD) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRD by the input capture signals. When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the ICFD will be set out, data transference to the ICRD will not be performed.
Page 396 Bit 2: Output Comparing Flag B (OCFB) This is a status flag indicating the fact that the FRC and the OCRB have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware.
Page 397: Timer Control Register X (Tcrx)
17.2.6 Timer Control Register X (TCRX) Bit : IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value : R/W : The TCRX is an 8-bit read/write register which works to select the input capture signal edge, to designate the buffer operation and to select the inputting clock for the FRC. The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
Page 398 Bit 4: Input Capture Signal Edge Selection D (IEDGD) This bit works to select the rising edge or falling edge of the input capture signal D (FTID). Bit 4 IEDGD Description Captures the falling edge of the input capture signal D (Initial value) Captures the rising edge of the input capture signal D Bit 3: Buffer Enabling A (BUFEA)
Page 399: Timer Output Comparing Control Register (Tocr)
17.2.7 Timer Output Comparing Control Register (TOCR) Bit : ICSB ICSC ICSD OSRS OLVLA OLVLB Initial value : R/W : The TOCR is an 8-bit read/write register which works to select input capture signals and output comparing output level, to permit output comparing outputs and to control switching over of the access of the OCRA and OCRB.
Page 400 Bit 4: Selecting the Output Comparing Register (OCRS) The addresses of the OCRA and OCRB are the same. The OCRS works to control which register to choose when reading/writing this address. The choice will not influence the operation of the OCRA and OCRB. Bit 4 OCRS Description...
Page 401 Bit 0: Output Level B (OLVLB) This bit works to select the output level to output through the FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB). Bit 0 OLVLB Description Low level (Initial value) High level Rev.
Page 402: Module Stop Control Register (Mstpcr)
17.2.8 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR consists of twin 8-bit read/write registers and it works to control the module stop mode.
Page 403: Operation
17.3 Operation 17.3.1 Operation of the Timer X1 (1) Output Comparing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX.
Page 404: Counting Timing Of The Frc
17.3.2 Counting Timing of the FRC The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the inputting clock can be selected from among three different types of clocks (φ/4, φ/16 and φ/64) and the DVCFG.
Page 405: Output Comparing Signal Outputting Timing
17.3.3 Output Comparing Signal Outputting Timing When a comparing match occurs, the output level having been set by the OLVL of the TOCR is output through the output comparing signal outputting pins (FTOA and FTOB). Figure 17.5 shows the timing chart in case of the output comparing signal outputting A. OCRA Comparing match signal...
Page 406: Input Capture Signal Inputting Timing
17.3.5 Input Capture Signal Inputting Timing (1) Input Capture Signal Inputting Timing As for the input capture signal inputting, rising or falling edge is selected by settings of the IEDGA through IEDGD bits of the TCRX. Figure 17.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD = 1).
Page 407: Input Capture Flag (Icfa Through Icfd) Setting Up Timing
Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up corresponding to the designated edge change of respective input capture signals. For example, when using the ICRC as the buffer register for the ICRA, when an edge change having been designated by the IEDGC bit is detected with the input capture signals C and if the ICIEC bit is duly set, an interrupt request will be issued.
Page 408: Output Comparing Flag (Ocfa And Ocfb) Setting Up Timing
17.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing The OCFA and OCFB are being set to 1 by the comparing match signal being output when the values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last state of the value match (the timing of the FRC's updating the matching count reading).
Page 409: Operation Mode Of The Timer X1
17.4 Operation Mode of the Timer X1 Table 17.4 indicated below shows the operation mode of the Timer X1. Table 17.4 Operation Mode of the Timer X1 Operation Module mode Reset Active Sleep Watch Subactive Standby Subsleep stop Reset Functions Functions Reset Reset...
Page 410: Interrupt Causes
17.5 Interrupt Causes Total seven interrupt causes exist with the Timer X1, namely, ICIA through ICID, OCIA, OCIB and FOVI. Table 17.5 given below lists the contents of respective interrupt causes. Respective interrupt requests can be permitted or prohibited by setting of respective interrupt enabling bits of the TIER.
Page 411: Exemplary Uses Of The Timer X1
17.6 Exemplary Uses of the Timer X1 Figure 17.12 indicated below shows an example of outputting at optional phase difference of the pulses of the 50% duty. For this setting, follow the procedures listed below. (1) set the CCLRA bit of the TCSRX to "1". (2) Each time a comparing match occurs, the OLVIA bit and the OLVLB bit are reversed by use of the software.
Page 412: Precautions When Using The Timer X1
17.7 Precautions when Using the Timer X1 Pay great attention to the fact that the following competitions and operations occur during operation of the Timer X1. 17.7.1 Competition between Writing and Clearing with the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle, writing into the FRC will not be effected and the priority will be given to clearing of the FRC.
Page 413: Competition Between Writing And Counting Up With The Frc
17.7.2 Competition between Writing and Counting Up with the FRC When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the counting up will not be effected and the priority will be given to count writing. Figure 17.14 shows the timing chart in this case.
Page 414: Competition Between Writing And Comparing Match With The Ocr
17.7.3 Competition between Writing and Comparing Match with the OCR When a comparing match occurs under the T2 state where the OCRA and OCRB are under the writing cycle, the priority will be given to writing of the OCR and the comparing match signal will be prohibited.
Page 415: Changing Over The Internal Clocks And Counter Operations
17.7.4 Changing Over the Internal Clocks and Counter Operations Depending on the timing of changing over the internal clocks, the FRC may count up. Table 17.6 indicated below shows the relations between the timing of changing over the internal clocks (Re-writing of the CKS1 and CKS0) and the FRC operations.
Page 416 Re-writing timing for the CKS1 and CKS0 FRC operation High → Low level Clock before changeover the changeover Clock after the changeover Count clock Re-writing of the CKS1 and CKS0 High → High level Clock before changeover the changeover Clock after the changeover Count clock...
Page 417 Rev. 2.0, 11/00, page 390 of 1037...
Page 418: Section 18 Watchdog Timer (Wdt)
Section 18 Watchdog Timer (WDT) 18.1 Overview This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal.
Page 419: Block Diagram
18.1.2 Block Diagram Figure 18.1 shows block diagram of WDT. / 64 WOVI / 128 (Interrupt request signal) Interrupt / 512 Clock control Overflow Clock Internal NMI select / 2048 • interrupt request signal Reset / 8192 control / 32768 / 131072 Internal reset signal * Internal clock...
Page 420: Register Configuration
18.1.3 Register Configuration The WDT has two registers, as summarized in table 18.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 18.2 WDT Registers Address Name Abbrev. Initial Value Write Read Watchdog timer WTCSR R/ (W) H'00 H'FFBC H'FFBC...
Page 421: Register Descriptions
18.2 Register Descriptions 18.2.1 Watchdog Timer Counter (WTCNT) Bit : Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
Page 422 Bit 7: Overflow Flag (OVF) A status flag that indicates that WTCNT has overflowed from H'FF to H'00. Bit 7 Description [Clearing conditions] (Initial value) (1) Write 0 in the TME bit (2) Read WTCSR when OVF = 1, then write 0 in OVF [Setting condition] When WTCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is...
Page 423 Bit 3: Reset or NMI (RST/ Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in watchdog timer mode. Bit 3 RST/ Description 1,0, 1,0, An NMI interrupt request is generated (Initial value) An internal reset request is generated Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0) These bits select an internal clock source, obtained by dividing the system clock (φ) for input to WTCNT.
Page 424: System Control Register (Syscr)
18.2.3 System Control Register (SYSCR) Bit : — — INTM1 INTM0 XRST NMIEG1 NMIEG0 — Initial value : R/W : — — — Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Page 425 <WTCNT write> H'5A Write data Address : H'FFBC <WTCSR write> H'A5 Write data Address : H'FFBC Figure 18.2 Format of Data Written to WTCNT and WTCSR (2) Reading WTCNT and WTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for WTCSR, and H'FFBD for WTCNT.
Page 426: Operation
18.3 Operation 18.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/ and TME bits in WTCSR to 1. Software must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. This ensures that WTCNT does not overflow while the system is operating normally.
Page 427: Interval Timer Operation
18.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/ bit in WTCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 18.4.
Page 428: Timing Of Setting Of Overflow Flag (Ovf)
18.3.3 Timing of Setting of Overflow Flag (OVF) The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 18.5. If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested.
Page 429: Interrupts
18.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request.
Page 430: Changing Value Of Cks2 To Cks0
18.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
Page 431 Rev. 2.0, 11/00, page 404 of 1037...
Page 432: Section 19 8-Bit Pwm
Section 19 8-Bit PWM 19.1 Overview The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to control a reel motor or loading motor. 19.1.1 Features • Conversion period: 256-state • Duty control method 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the 8-bit PWM (1 channel).
Page 433: Pin Configuration
19.1.3 Pin Configuration Table 19.1 shows the 8-bit PWM pin configuration. Table 19.1 Pin Configuration Name Abbrev. Function 8-bit PWM square-wave output pin PWM0 Output 8-bit PWM square-wave output 0 8-bit PWM square-wave output pin PWM1 Output 8-bit PWM square-wave output 1 8-bit PWM square-wave output pin PWM2 Output...
Page 434: Register Descriptions
19.2 Register Descriptions 19.2.1 Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) (1) PWR0 Bit : PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 Initial value : R/W : (2) PWR1 Bit : PW17 PW16 PW15 PW14 PW13...
Page 435: 8-Bit Pwm Control Register (Pw8Cr)
19.2.2 8-bit PWM Control Register (PW8CR) Bit : — — — — PWC3 PWC2 PWC1 PWC0 Initial value : — — — — R/W : The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM functions. PW8CR is initialized to H'00 by a reset. Bits 7 to 4: Reserved They are always read as 1.
Page 436: Port Mode Register 3 (Pmr3)
19.2.3 Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching is specified for each bit. The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset.
Page 437: Module Stop Control Register (Mstpcr)
19.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle and transits to the module stop mode.
Page 438: 8-Bit Pwm Operation
19.3 8-Bit PWM Operation The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width determined by the data registers (PWR). The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter. Figure 19.2 shows the output waveform example of 8-bit PWM.
Page 439 Rev. 2.0, 11/00, page 412 of 1037...
Page 440: Section 20 12-Bit Pwm
Section 20 12-Bit PWM 20.1 Overview The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 20.1.1 Features Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the pulse-pitch control method (periodically overriding part of the output).
Page 441: Block Diagram
20.1.2 Block Diagram Figure 20.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. Low-frequency components are reduced because the two quantizing pulses have different frequencies.
Page 442: Pin Configuration
20.1.3 Pin Configuration Table 20.1 shows the 12-bit PWM pin configuration. Table 20.1 Pin Configuration Name Abbrev. Function Capstan mix CAPPWM Output 12-bit PWM square-wave output Drum mix DRMPWM 20.1.4 Register Configuration Table 20.2 shows the 12-bit PWM register configuration. Table 20.2 12-Bit PWM Registers Name Abbrev.
Page 443: Register Descriptions
20.2 Register Descriptions 20.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) (1) CPWCR Bit : CPOL CHiZ CH/L CSF/DF CCK2 CCK1 CCK0 Initial value : R/W : (2) DPWCR Bit : DPOL DHiZ DH/L DSF/DF DCK2 DCK1 DCK0 Initial value : R/W : CPWCR is the PWM output control register for the capstan motor.
Page 444 Bits 5 and 4: PWM Pin Output (HiZ, H/L) When bit DC is set to 1, the 12-bit PWM output pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is not affected by bit POL. In power-down modes, the 12-bit PWM circuit and pin statuses are retained.
Page 445 Bit 2 to 0: Carrier Frequency Select (CK2 to CK0) Selects the carrier frequency of the PWM modulated signal. Do not set them to 111. Bit 2 Bit 1 Bit 0 Description φ2 φ4 φ8 (Initial value) φ16 φ32 φ64 φ128 (Do not set) Rev.
Page 446: 12-Bit Pwm Data Registers (Cpwdr, Dpwdr)
20.2.2 12-Bit PWM Data Registers (CPWDR, DPWDR) (1) CPWDR Bit : — — — — CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Initial value : R/W : — — — — (2) DPWDR Bit : —...
Page 447: Module Stop Control Register (Mstpcr)
20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When the MSTP1 bit is set to 1, the 12-bit PWM and Servo circuit, stops their operation upon completion of the bus cycle and transits to the module stop mode.
Page 448: Operation
20.3 Operation 20.3.1 Output Waveform The PWM signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. When Vcc/2 is set as the reference value, the following conditions apply: • When the motor is running at the correct sped and phase, the PWM signal is output with a 50% duty cycle.
Page 449 Figure 20.2 Sample Waveform Output by 12-Bit PWM (4 Bits) Rev. 2.0, 11/00, page 422 of 1037...
Page 450: Section 21 14-Bit Pwm
Section 21 14-Bit PWM 21.1 Overview The 14-bit PWM is a pulse division type PWM which can be used for V-synthesizer, etc. 21.1.1 Features Features of the 14-bit PWM are given below: • Choice of two conversion periods A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversion period of 16384/φ...
Page 451: Block Diagram
21.1.2 Block Diagram Figure 21.1 shows a block diagram of the 14-bit PWM. PWCR PWDRL PWDRU PWM waveform PWM14 generator [Legend] PWCR : PWM control register PWDRL : PWM data register L PWDRU : PWM data register U PWM14 : PWM14 output pin Figure 21.1 Block Diagram of 14-Bit PWM 21.1.3 Pin Configuration...
Page 452: Register Configuration
21.1.4 Register Configuration Table 21.2 shows the 14-bit PWM register configuration. Table 21.2 14-Bit PWM Registers Name Abbrev. Size Initial Value Address* PWM control register PWCR Byte H'FE H'D122 PWM data register U PWDRU Byte H'00 H'D121 PWM data register L PWDRL Byte H'00...
Page 453: Register Descriptions
21.2 Register Descriptions 21.2.1 PWM Control Register (PWCR) Bit : — — — — — — — PWCR0 Initial value : — — — — — — — R/W : The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM functions.
Page 454: Pwm Data Registers U And L (Pwdru, Pwdrl)
21.2.2 PWM Data Registers U and L (PWDRU, PWDRL) (1) PWDRU Bit : — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value : R/W : — — (2) PWDRL Bit : PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value : R/W : PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN...
Page 455: Module Stop Control Register (Mstpcr)
21.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that control the module stop mode functions.
Page 456: 14-Bit Pwm Operation
21.3 14-Bit PWM Operation When using the 14-bit PWM, set the registers in this sequence: (1) Set bit PMR40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for PWM output. (2) Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/φ...
Page 457 Rev. 2.0, 11/00, page 430 of 1037...
Page 458: Section 22 Prescalar Unit
Section 22 Prescalar Unit 22.1 Overview The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ as a clock source and a 5-bit counter that uses φW as a clock source. 22.1.1 Features • Prescalar S (PSS): Generates frequency division clocks that are input to peripheral functions.
Page 459: Block Diagram
22.1.2 Block Diagram Figure 22.1 shows a block diagram of the prescalar unit. PWM3 PWM2 PWM1 Stable oscillation PWM0 wait time count output 6 bits 8 bits Prescalar S /131072 to /2 18-bit free running counter (FRC) 8 bits IC pin TMOW w/32 ICR1...
Page 460: Pin Configuration
22.1.3 Pin Configuration Table 22.1 shows the pin configuration of the prescalar unit. Table 22.1 Pin Configuration Name Abbrev. Function ,& Input capture input Input Prescalar unit input capture input pin Frequency division clock TMOW Output Prescalar unit frequency division clock output output pin 22.1.4...
Page 461: Registers
22.2 Registers 22.2.1 Input Capture Register 1 (ICR1) Bit : ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 Initial value : R/W : Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge ,&...
Page 462 Bit 6: Input Capture Interrupt Enable (ICIE) ,& When ICIF was set to 1 by the input capture according to the edge of the pin, ICIE enables and disables the generation of an input capture interrupt. Bit 6 ICIE Description Disables the generation of an input capture interrupt (Initial value) Enables the generation of an input capture interrupt...
Page 463 Bits 2 to 0: Frequency Division Clock Output Select (DCS2 to DCS0) DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW pin. Bit 2 Bit 1 Bit 0 DCS2 DCS1 DCS0 Description Outputs PSS, φ/32 (Initial value) Outputs PSS, φ/16 Outputs PSS, φ/8...
Page 464: Port Mode Register 1 (Pmr1)
22.2.3 Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
Page 465: Operation
22.4 Operation 22.4.1 Prescalar S (PSS) The PSS is a 17-bit counter that uses the system clock (φ=fosc) as an input clock and generates the frequency division clocks (φ/131072 to φ/2) of the peripheral function. The low-order 17 bits of the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one clock.
Page 466: Prescalar W (Psw)
22.4.2 Prescalar W (PSW) PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock of the timer A. In this case, the timer A functions as a clock time base. When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins.
Page 467: 8-Bit Pwm
22.4.4 8-Bit PWM This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It counts the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and loading motors.
Page 468: Section 23 Serial Communication Interface 1 (Sci1)
Section 23 Serial Communication Interface 1 (SCI1) 23.1 Overview The serial communication interface 1 (SCI1) can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 23.1.1 Features SCI1 features are listed below. (1) Choice of asynchronous or clock synchronous serial communication mode (a) Asynchronous mode •...
Page 469 (2) Full-duplex communication capability • The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously • Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data (3) Built-in baud rate generator allows any bit rate to be selected (4) Choice of serial clock source: internal clock from baud rate generator or external clock from SCK1 pin...
Page 470: Block Diagram
23.1.2 Block Diagram Figure 23.1 shows a block diagram of the SCI1. Module data bus RDR1 TDR1 SCMR1 BRR1 SSR1 SCR1 Baud rate generator SMR1 Transmission/ reception control Parity gfeneration Clock Parity check External clock SCK1 [Legend] : Receive shift register RDR1 : Receive data register1 : Transmit shift register...
Page 471: Pin Configuration
23.1.3 Pin Configuration Table 23.1 shows the serial pins used by the SCI1. Table 23.1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 1 SCK1 SCI1 clock input/output Receive data pin 1 Input SCI1 receive data input Transmit data pin 1 Output SCI1 transmit data output 23.1.4...
Page 472: Register Descriptions
23.2 Register Descriptions 23.2.1 Receive Shift Register (RSR) Bit : R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI1 sets serial data input from the SI1 pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 473: Transmit Shift Register (Tsr)
23.2.3 Transmit Shift Register (TSR) Bit : R/W : — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI1 first transfers transmit data from TDR1 to TSR, then sends the data to the SO1 pin starting with the LSB (bit 0).
Page 474: Serial Mode Register (Smr1)
23.2.5 Serial Mode Register (SMR1) Bit : STOP CKS1 CKS0 Initial value : R/W : SMR1 is an 8-bit register used to set the SCI1's serial transfer format and select the baud rate generator clock source. SMR1 can be read or written to by the CPU at all times. SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
Page 475 Bit 5: Parity Enable (PE) In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 Description Parity bit addition and checking disabled...
Page 476 Bit 3: Stop Bit Length (STOP) Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added.
Page 477: Serial Control Register (Scr1)
Bits 1 and 0: Clock Select 1 and 0 (CKS1, CKS0) These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 23.2.8, Bit Rate Register.
Page 478 Bit 6: Receive Interrupt Enable (RIE) Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR1 and the RDRF flag in SSR1 is set to 1. Bit 6 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*...
Page 479 Bit 3: Multiprocessor Interrupt Enable (MPIE) Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR1 set to 1. The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 480: Serial Status Register (Ssr1)
Bit 1 Bit 0 CKE1 CKE0 Description Asynchronous mode Internal clock/SCK1 pin functions as I/O port Clock synchronous Internal clock/SCK1 pin functions as serial mode clock output Asynchronous mode Internal clock/SCK1 pin functions as clock output Clock synchronous Internal clock/SCK1 pin functions as serial mode clock output Asynchronous mode...
Page 481 Bit 7: Transmit Data Register Empty (TDRE) Indicates that data has been transferred from TDR1 to TSR and the next serial data can be written to TDR1. Bit 7 TDRE Description [Clearing conditions] When 0 is written in TDRE after reading TDRE = 1 [Setting conditions] (Initial value) (1) When the TE bit in SCR1 is 0...
Page 482 Bit 5: Overrun Error (ORER) Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description [Clearing conditions] (Initial value) When 0 is written in ORER after reading ORER = 1 [Setting conditions] When the next serial reception is completed while RDRF = 1 Notes: 1.
Page 483 Bit 3: Parity Error (PER) Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing conditions] (Initial value) When 0 is written in PER after reading PER = 1 [Setting conditions] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/...
Page 484: Bit Rate Register (Brr1)
Bit 1: Multiprocessor Bit (MPB) When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 Description [Clearing conditions] (Initial value)* When data with a 0 multiprocessor bit is received [Setting conditions] When data with a 1 multiprocessor bit is received...
Page 485 Table 23.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) −0.04 −0.26 0.03 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 −0.70 1200 0.16 0.00...
Page 486 Operating Frequency φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) −0.44 −0.07 0.08 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00 0.16 2400 0.16 0.00 0.00 0.16 4800 0.16 0.00 0.00...
Page 487 Table 23.4 BRR1 Settings for Various Bit Rates (Clock Synchronous Mode) Operating Frequency φ (MHz) Rate (bits/s)         2.5 k 10 k 25 k 50 k 100 k 250 k 500 k 2.5 M Note: As far as possible, the setting should be made so that the error is no more than 1%.
Page 488 The BRR1 setting is found from the following equations. • Asynchronous mode: φ ×10 6−1 ×B 2n−1 64×2 • Clock synchronous mode: φ ×10 6−1 ×B 2n−1 8×2 Where B: Bit rate (bits/s) N: BRR1 setting for baud rate generator (0 ≤ N ≤ 255) φ: Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.)
Page 489 Table 23.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) 62500 2.097152 65536 2.4576 76800 93750 3.6864 115200 125000 4.9152 153600 156250 187500 6.144 192000 7.3728 230400 250000 9.8304 307200 312500 Rev. 2.0, 11/00, page 462 of 1037...
Page 490 Table 23.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 83750...
Page 491: Serial Interface Mode Register (Scmr1)
23.2.9 Serial Interface Mode Register (SCMR1) Bit : — — — — SDIR SINV — SMIF Initial value : R/W : — — — — — SCMR1 is an 8-bit readable/writable register used to select SCI1 functions. SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
Page 492: Module Stop Control Register (Mstpcr)
Bit 1: Reserved This bit cannot be modified and is always read as 1. Bit 0: Serial Communication Interface Mode Select (SMIF) 1 should not be written in this bit. Bit 0 SMIF Description Normal SCI mode (Initial value) Reserved mode 23.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL...
Page 493: Operation
23.3 Operation 23.3.1 Overview The SCI1 can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR1 as shown in table 23.8.
Page 494 Table 23.8 SMR1 Settings and Serial Transfer Format Selection SMR1 Settings SCI1 Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multiproc Parit Stop bit STOP Mode length -essor bit y bit length Asynchro- 8-bit 1 bit nous mode data 2 bits...
Page 495: Operation In Asynchronous Mode
23.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis.
Page 496 (1) Data Transfer Format Table 23.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR1. Table 23.10 Serial Transfer Formats (Asynchronous Mode) SMR1 Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP...
Page 497 (2) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK1 pin can be selected as the SCI1's serial clock, according to the setting of the C/ bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI1 clock source selection, see table 23.9.
Page 498 (3) Data Transfer Operations (a) SCI1 Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI1 as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 499 (b) Serial Data Transmission (Asynchronous Mode) Figure 23.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI1 initialization: Initialization The SO1 pin is automatically designated as the transmit data output pin. Start transmission SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag...
Page 500 In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission.
Page 501 Data Data Start Parity Stop Parity Stop Start Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR1 and TXI interrupt request TEI interrupt request request TDRE flag cleared to 0 generated generated generated in TXI interrupt handling routine 1 frame Figure 23.6 Example of Operation in Transmission in Asynchronous Mode...
Page 502 (c) Serial Data Reception (Asynchronous Mode) Figure 23.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI1 initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception [2][3] Receive error handling and break...
Page 503 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 PER=1 Parity error handling Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 23.7 Sample Serial Reception Data Flowchart (2) Rev.
Page 504 In serial reception, the SCI1 operates as described below. [1] The SCI1 monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
Page 505: Multiprocessor Communication Function
Figure 23.8 shows an example of the operation for reception in asynchronous mode. Data Data Start Parity Stop Start Parity Stop Idle state (mark state) RDRF RXI interrupt RDR1 data read ERI interrupt request request and RDRF flag generated by framing cleared to 0 in generation error...
Page 506 (1) Data Transfer Format There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 23.10. (2) Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving Receiving Receiving...
Page 507 SCI1 initialization: Initialization The SO1 pin is automatically designated as the transmit data output pin. Start transmission SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to Read TDRE flag in SSR1 TDR1.
Page 508 In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission.
Page 509 Figure 23.11 shows an example of SCI1 operation for transmission using a multiprocessor format. Multi- Multi- Data Data processor Start processor Stop Stop Start bit 1 Idle state (mark state) TDRE TEND Data written to TDR1 and TXI interrupt request TXI interrupt TEI interrupt TDRE flag cleared to 0...
Page 510 Initialization SCI1 initialization: The SI1 pin is automatically designated as the receive data input pin. Start reception ID reception cycle: Set the MPIE bit in SCR1 to 1. Set MPIE bit in SCR1 to 1 SCI1 status check, ID reception and Read ORER and FER flags in SSR1 comparison: Read SSR1 and check that the RDRF flag...
Page 511 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 23.12 Sample Multiprocessor Serial Reception Flowchart (2) Figure 23.13 shows an example of SCI1 operation for multiprocessor format reception. Rev.
Page 512 Data (ID1) Data (Data 1) Start Stop Start Stop Idle state (mark state) MPIE RDRF RDR1 value MPIE=0 RXI interrupt RDR1 data read If not this station's RXI interrupt request request (multi- and RDRF flag ID, MPIE bit is set is not generated, and processor RDR1 retains its state...
Page 513: Operation In Clock Synchronous Mode
23.3.4 Operation in Clock Synchronous Mode In clock synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI1, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
Page 514 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, select an external clock as the clock source.
Page 515 (b) Serial Data Transmission (Clock Synchronous Mode) Figure 23.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI1 initialization: Initialization The SO1 pin is automatically designated as the transmit data output pin. Start transmission SCI1 status check and transmit data write: Read SSR1 and check that the TDRE flag...
Page 516 In serial transmission, the SCI1 operates as described below. [1] The SCI1 monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR. [2] After transferring data from TDR1 to TSR, the SCI1 sets the TDRE flag to 1 and starts transmission.
Page 517 (c) Serial Data Reception (Clock Synchronous Mode) Figure 23.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
Page 518 SCI1 initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception Receive error handling: [2][3] IF a receive error occurs, read the ORER flag in SSR1, and after performing the Read ORER flag in SSR1 appropriate error handling, clear the ORER flag to 0.
Page 519 In serial reception, the SCI1 operates as described below. [1] The SCI1 performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI1 checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR1.
Page 520 SCI1 initialization: Initialization The SO1 pin is designated as the transmit data output pin, and the SI1 pin is Start transfer designated as the receive data input pin, enabling simultaneous transmit and receive Read TDRE flag in SSR1 operations. SCI1 status check and transmit data write: TDRE=1 Read SSR1 and check that the TDRE flag is set to 1, then write transmit data to TDR1...
Page 521: Sci1 Interrupts
23.4 SCI1 Interrupts The SCI1 has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 23.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR1.
Page 522: Usage Notes
23.5 Usage Notes The following points should be noted when using the SCI1. (1) Relation between Writes to TDR1 and the TDRE Flag The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred from TDR1 to TSR.
Page 523 Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set to 1). Consequently, PCR and PDR for the port corresponding to the SO1 pin should first be set to 1.
Page 524 Thus the receive margin in asynchronous mode is given by equation (1) below. D − 0.5 ) − (L−0.5) F − (1+F) × 100% M = (0.5− …..(1) Where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation...
Page 525 Rev. 2.0, 11/00, page 498 of 1037...
Page 526: Section 24 Serial Communication Interface 2 (Sci2)
Section 24 Serial Communication Interface 2 (SCI2) 24.1 Overview The serial communication interface 2 (SCI2) that has a 32-byte data buffer carries out clocked synchronous serial transmission of 32 bytes by a single operation. 24.1.1 Features SCI2 features are listed below. •...
Page 527: Block Diagram
24.1.2 Block Diagram Figure 24.1 shows a block diagram of the SCI2. Internal clock /256, /64, /32, /16, /8, /4, /2 SCK2 SCK2 STAR STRB Transmit/ EDAR receive control SCR2 circuit SCSR2 Data buffer (32 bytes) Interrupt generation circuit Interrupt request [Legend] STAR : Starting address register...
Page 528: Pin Configuration
24.1.3 Pin Configuration Table 24.1 shows pin configuration of the SCI2. Table 24.1 Pin Configuration Name Abbrev. Function SCI2 Clock SCK2 SCI2 clock input/output pin SCI2 Data input Input SCI2 receive data input pin SCI2 Data output Output SCI2 transmit data output pin SCI2 Strobe STRB Output...
Page 529: Register Descriptions
24.2 Register Descriptions 24.2.1 Starting Address Register (STAR) Bit : STA4 STA3 STA2 STA1 STA0 — — — Initial value : R/W : — — — The STAR is a readable/writable register that specifies the transfer starting address within the address space (H'FFD0C0 to H'FFD0DF) to which a 32-byte data buffer is assigned.
Page 530: Serial Control Register 2 (Scr2)
24.2.3 Serial Control Register 2 (SCR2) Bit : — TEIE ABTIE GAP1 GAP0 CKS2 CKS1 CKS0 Initial value : — R/W : The SCR 2 is a readable/writable register that enables or disables generation of SCI2 interrupt and selects an data transfer interval and transfer clock when an internal clock is used. The SCR2 is initialized to H'20 by a reset.
Page 531: Serial Control Status Register 2 (Scsr2)
Bits 4 and 3: Transmit Data Interval Select 1 and 0 (GAP1, GAP0) When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal retains the low level.
Page 532 Bit 7: Transmit End Interrupt Request Flag (TEI) Indicates that data transmission or reception has been completed. Bit 7 Description [Clearing condition] (Initial value) When 0 is written after reading 1 [Setting condition] When transmission or reception has been completed Bits 6 and 5: Reserved When each bit is read, 1 is read at all times.
Page 533 Bit 3: Overrun Error Flag (ORER) The ORER indicates an occurrence of overrun error while an external clock is used. When excessive pulses are overlapped with the normal transfer clock caused by external noise, etc. during transmission, this bit is set to 1. At this time data transfer cannot be assured. When a clock is input after completion of transmission, it is also found to be in the state of overrun and this bit is set to 1.
Page 534: Module Stop Control Register (Mstpcr)
Bit 0: Start Flag (STF) The STF controls the start of transfer operations. When this bit is set to 1 and PMR30 of PMR3 is 0, transfer operation of the SCI2 is started. When PMR30 of PMR3 is 1, the low level of the pin is detected and transfer is started.
Page 535: Operation
24.3 Operation The SCI2, comprising 32 bytes serial data buffer, can continuously transmit a maximum of 32 bytes data by a single operation, synchronized with clock pulse. Installation of a register enables to select transmit, receive, or simultaneous transmit/receive. When transmit is set, the value of serial data buffer is retained even after completion of transmission.
Page 536 Figure 24.2 Transfer Format (Transfer Data without Intervals) Rev. 2.0, 11/00, page 509 of 1037...
Page 537 Figure 24.3 Transfer Format (Transfer Data with Intervals) Rev. 2.0, 11/00, page 510 of 1037...
Page 538: Data Transfer Operations
24.3.3 Data Transfer Operations (1) SCI2 Initialization To carry out data transfer, first initialize the SCI2 using software. Initialization is performed as described below: (1) Use PMR2, PMR3, STAR, EDAR and SCR2 to set the pin and transmission mode while STF of SCSR2 is set to 0.
Page 539 (2) Transmit Operations Transmit operations are performed as described below: (1) Set PMR26 and PMR27 of PMR2 to 1 and set them to the SO2 and SCK2 pins, respectively. Set the SO2 pin to the open drain output using PMR20 of PMR2 and set them to the and STRB pins, respectively, using PMR30 and PMR31 of PMR3, as necessary.
Page 540 (3) Receive Operations Receive operations are performed as described below: (1) Set PMR25 and PMR27 of PMR2 to 1 and set them to the SI2 and SCK2 pins, respectively. Set them to the pin, using PMR30 of PMR3 as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2.
Page 541 (4) Simultaneous Transmit/Receive Operations Simultaneous transmit/receive operations are performed as described below: (1) Set PMR25, PMR26 and PMR27 of PMR2 to 1 and set them to the SI2, SO2 and SCK2 pins, respectively. Set the SO2 pin to open drain output, using PMR20 of PMR2, and set them to the STRB pins, respectively, using PMR30 and PMR31, as necessary.
Page 542: Interrupt Sources
24.4 Interrupt Sources An interrupt source of the SCI2 is transmission cutoff by completion of transmission and the pin, to which different vector addresses are assigned. On completion of data transfer, TEI of SCSR2 is set to 1, and transfer-end interrupt request is generated.
Page 543 Rev. 2.0, 11/00, page 516 of 1037...
Page 544: Section 25 I C Bus Interface (Iic)
Section 25 I C Bus Interface (IIC) 25.1 Overview The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 545: Block Diagram
25.1.2 Block Diagram Figure 25.1 shows a block diagram of the I C bus interface. Figure 25.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to input pins depend on the power (Vcc) voltage of this LSI.
Page 546: Pin Configuration
(Master) This chip (Slave 1) (Slave 2) Figure 25.2 I C Bus Interface Connections (Example: This Chip as Master) 25.1.3 Pin Configuration Table 25.1 summarizes the input/output pins used by the I C bus interface. Table 25.1 I C Bus Interface Pins Name Abbrev.
Page 547: Register Configuration
25.1.4 Register Configuration Table 25.2 summarizes the registers of the I C bus interface. Table 25.2 Register Configuration Name Abbrev. Initial Value Address C bus control register ICCR H'01 H'D158 C bus status register ICSR H'00 H'D159 C bus data register ICDR —...
Page 548: Register Descriptions
25.2 Register Descriptions 25.2.1 C Bus Data Register (ICDR) Bit : ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value : — — — — — — — — R/W : ICDRR Bit : ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0...
Page 549 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
Page 550 If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Page 551: Slave Address Register (Sar)
25.2.2 Slave Address Register (SAR) Bit : SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 552 Bit 0: Format Select (FS) Used together with the FSX bit in SARX to select the communication format. • I C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode.
Page 553: Second Slave Address Register (Sarx)
25.2.3 Second Slave Address Register (SARX) Bit : SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 Initial value : R/W : SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
Page 554: C Bus Mode Register (Icmr)
25.2.4 C Bus Mode Register (ICMR) Bit : WAIT CKS2 CKS1 CKS0 Initial value : R/W : ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count.
Page 555 Bit 6: Wait Insertion Bit (WAIT) Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
Page 556 Bits 5 to 3: Transfer Clock Select (CKS2 to CKS0) These bits, together with the IICX bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bit 6 Bit 5 Bit 4...
Page 557 Bits 2 to 0: Bit Counter (BC2 to BC0) Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit.
Page 558: C Bus Control Register (Iccr)
25.2.5 C Bus Control Register (ICCR) Bit : IEIC ACKE BBSY IRIC Initial value : R/(W) * R/W : Note: * Only 0 can be written to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I...
Page 559 Bit 5: Master/Slave Select (MST) Bit 4: Transmit/Receive Select (TRS) MST selects whether the I C bus interface operates in master mode or slave mode. TRS selects whether the I C bus interface operates in transmit mode or receive mode. In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode.
Page 560 Bit 4 Description Receive mode (Initial value) [Clearing conditions] (1) When 0 is written by software (in cases other than setting condition 3) (2) When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3) (3) When bus arbitration is lost after transmission is started in I C bus format master mode...
Page 561 Bit 2: Bus Busy (BBSY) The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1.
Page 562 Bit 1 IRIC Description Waiting for transfer, or transfer in progress (Initial value) [Clearing condition] (1) When 0 is written in IRIC after reading IRIC = 1 Interrupt requested [Setting conditions] C bus format master mode (1) When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) (2) When a wait is inserted between the data and acknowledge bit when WAIT = 1...
Page 563 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
Page 564 Table 25.3 Flags and Transfer States BBSY ESTP STOP IRTR AASX AL ACKB State Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match...
Page 565: C Bus Status Register (Icsr)
25.2.6 C Bus Status Register (ICSR) Bit : ESTP STOP IRTR AASX ACKB Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W : Note: * Only 0 can be written to clear the flag. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control.
Page 566 Bit 6: Normal Stop Condition Detection Flag (STOP) Indicates that a stop condition has been detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP Description No normal stop condition (Initial value) [Clearing condition] (1) When 0 is written in STOP after reading STOP = 1 (2) When the IRIC flag is cleared to 0 In I...
Page 567 Bit 5: I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag (IRTR) Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC* activation is possible.
Page 568 Bit 4: Second Slave Address Recognition Flag (AASX) In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected.
Page 569 Bit 2: Slave Address Recognition Flag (AAS) In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS.
Page 570: Serial/Timer Control Register (Stcr)
Bit 0: Acknowledge Bit (ACKB) Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read.
Page 571 Bit 5: I C Controller Reset (IICRST) This bit controls the initialization of the internal state of the I C bus interface. When the I C bus interface operating mode is hung because of communications error, and the IICRST bit is then set to 1, the I C bus interface controller is initialized of the internal state, and this allows the internal state of the I...
Page 572: Module Stop Control Register (Mstpcr)
25.2.8 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
Page 573: Operation
25.3 Operation 25.3.1 C Bus Data Format The I C bus interface has serial and I C bus formats. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figure 25.3. The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit.
Page 574: Master Transmit Operation
DATA DATA Figure 25.5 I C Bus Timing Table 25.4 I C Bus Data Format Symbols Start condition. The master device drives SDA from high to low while SCL is hig Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/ is 1, or from the master device to the slave device when R/...
Page 575 clearing, it can not be determine the end of transmission. The master device sequentially sends the transmission clock and the data written to ICDR using the timing shown in figure 25.6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal.
Page 576 Start condition Geberation (master output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 (master output) Slave address Data 1 (slave output) IRIC IRTR ICDR Data 1 address + R/ Note: Data write timing in ICDR ICDR Writing...
Page 577: Master Receive Operation
25.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. I C bus interface module consists of the data buffers of ICDRR and ICDRS, so data can be received continuously in master receive mode.
Page 578 [10] Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit to 1 to switch from receive mode to transmit mode. [11] Clear IRIC flag to 0 to release from the Wait State. [12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th receive clock pulse.
Page 579 (master output) Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 (slave output) Data 2 Data 3 Data 4 (master output) IRIC IRTR ICDR Data 1 Data 2 Data 3 User processing [9] IRIC clearance [6] ICDR read [7] IRIC clearance [9] IRIC Clearance [6] ICDR read...
Page 580: Slave Receive Operation
25.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode.
Page 581 Start condition issurance (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address Data 1 (Slave output) RDRF Interrupt request IRIC generated ICDRS Address + R/W ICDRR...
Page 582 (Master output) (Slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Master output) Data 1 Data 2 (Slave output) RDRF Interrupt Interrupt IRIC request request generated generated ICDRS Data 1 Data 2...
Page 583: Slave Transmit Operation
25.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. [1] Set bit ICE in ICCR to 1.
Page 584 Slave receive mode Slave transmit mode (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Slave output) Data 1 Data 2 (Master output) TDRE Interrupt Interrupt Interrupt IRIC...
Page 585: Iric Setting Timing And Scl Control
25.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred;...
Page 586 (a) When WAIT = 0, and FS = 0 or FSX = 0 (I C bus format, no wait) IRIC User Clear Write to ICDR (transmit) or processing IRIC read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC User...
Page 587: Noise Canceler
25.3.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 25.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 588 Start [1] Initialize Initialize [2] Test the status of the SCL and SDA lines. Read BBSY in ICCR BBSY = 0? [3] Select master transmit mode. Set MST = 1 and TRS = 1 in ICCR [4] Start condition issuance Write BBSY = 1 and SCP = 0 in ICCR [5] Wait for a start condition generation...
Page 589 Master receive mode Set TRS = 0 in ICCR [1] Select receive mode Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR [2] Start receiving. The first read is a dummy Read ICDR read. After reading ICDR, please clear IRIC immediately.
Page 590 Start Initialize Set MST=0 and TRS=0 in ICCR Set ACKB=0 in ICSR Read IRIC flag in ICCR IRIC=1? Read AAS and ADZ flags in ICSR AAS=1 and General call address processing ADZ=0? * Description omitted Read TRS bit in ICCR Slave transmit mode TRS=0? Last receive?
Page 591 Set transmit data for the second and Slave transmit mode subsequent bytes. Clear IRIC in ICCR Wait for 1 byte to be transmitted. Write transmit data in ICDR Test for end of transfer. Clear IRIC flag in ICCR Select slave receive mode. Dummy read (to release the SCL line).
Page 592: Initialization Of Internal State
25.3.9 Initialization of Internal State This I C is capable of forcibly initializing internal state of I C if deadlock develops during communication. The initialization is done by setting IICRST bit in STCR register, or clearing ICE bit. For details, see section 25.2.7, Serial/Time control Register (STCR). (1) Range of Initialization The following is initialized by this function: •...
Page 593 In order to avoid these troubles, the following procedures must be observed in initialization of (1) Implement initialization of internal state by setting IICRST bit or ICE bit. (2) Execute the stop condition issue instruction (setting BBSY = 0 and SCP = 0 to write) and wait for a duration equivalent to 2 clocks of the transfer rate.
Page 594: Usage Notes
25.4 Usage Notes (1) In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
Page 595 (5) The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If t (the time for SCL to go from low to V ) exceeds the time determined by the input clock of the I...
Page 596 Table 25.7 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Influence Specification φ = 5 MHz φ = 8 MHz φ = 10 MHz Item Indication (Max.) (Min.) Normal mode −1000 ←...
Page 597 (7) Precautions on reading ICDR at the end of master receive mode When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high level, thereby generating the stop condition.
Page 598 (8) Notes on Start Condition Issuance for Retransmission Figure 25.19 shows the timing of start conditon issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. After start condition issuance is done and determined the start condition, write the transmit data to ICDR. [1] Wait for end of 1-byte transfer IRIC=1 ? [2] Determine wheter SCL is low...
Page 599 (9) Notes on I C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below.
Page 600: Section 26 A/D Converter
Section 26 A/D Converter 26.1 Overview This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12 analog input channels to be selected. 26.1.1 Features A/D converter features are listed below. • 10-bit resolution • 12 input channels •...
Page 601: Block Diagram
26.1.2 Block Diagram Figure 26.1 shows a block diagram of the A/D converter. Internal data bus Reference Voltage 10-bit Hardware control circuit ADTRG (HSW timing generator) Vref ADTRG Chopper type Control circuit comparator Sample-and- hold circuit Interrupt request [Legend] : Software trigger A/D result register ADTRG, DFG : Hardware trigger : Hardware trigger A/D result register...
Page 602: Pin Configuration
26.1.3 Pin Configuration Table 26.1 summarizes the input pins used by the A/D converter. Table 26.1 A/D Converter Pins Name Abbrev. Function Analog power supply pin Input Analog block power supply Analog ground pin Input Analog block ground and A/D conversion reference voltage Analog input pin 0 Input...
Page 603: Register Configuration
26.1.4 Register Configuration Table 26.2 summarizes the registers of the A/D converter. Table 26.2 A/D Converter Registers Name Abbrev. Size Initial Value Address Software trigger A/D ADRH Byte H'00 H'D130 result register H Software trigger A/D ADRL Byte H'00 H'D131 result register L Hardware trigger A/D AHRH...
Page 604: Register Descriptions
26.2 Register Descriptions 26.2.1 Software-Triggered A/D Result Register (ADR) ADRH ADRL Bit : ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value : — — — — — — R/W : The software-triggered A/D result register (ADR) is a register that stores the result of an A/D conversion started by software.
Page 605 AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 26.3, Interface to Bus Master. AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Page 606: A/D Control Register (Adcr)
26.2.3 A/D Control Register (ADCR) Bit : — HCH1 HCH0 SCH3 SCH2 SCH1 SCH0 Initial value : R/W : — ADCR is a register that sets A/D conversion speed and selects analog input channel. When executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0. ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Page 607 States Instruction execution MOV.B WRITE Start flag Conversion frequency Conversion period (134 or 266 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is set. The CPU recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction.
Page 608 Bits 3 to 0: Software Channel Select (SCH3 to SCH0) These bits select the analog input channel that is converted by software triggering. When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register 0 (PMR0). For pin settings, see section 26.2.6, Port Mode Register 0 (PMR0). Bit 3 Bit 2 Bit 1...
Page 609: A/D Control/Status Register (Adcsr)
26.2.4 A/D Control/Status Register (ADCSR) Bit : SEND HEND ADIE BUSY SCNL — Initial value : R/(W) * R/(W) * — R/W : Note: * Only 0 can be written to bits 7 and 6, to clear the flag. The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D conversion, or check the status of the A/D converter.
Page 610 Bit 5: A/D Interrupt Enable (ADIE) Selects enable or disable of interrupt (ADI) generation upon A/D conversion end. Bit 5 ADIE Description Interrupt (ADI) upon A/D conversion end is disabled (Initial value) Interrupt (ADI) upon A/D conversion end is enabled Bit 4: Software A/D Start Flag (SST) Starts software-triggered A/D conversion and indicates or controls the end of conversion.
Page 611 Bit 2: Busy Flag (BUSY) During hardware- or external-triggered A/D conversion, if software attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY flag is set to 1. This flag is cleared when the hardware-triggered A/D result register (AHR) is read. Bit 2 BUSY Description...
Page 612: Trigger Select Register (Adtsr)
26.2.5 Trigger Select Register (ADTSR) Bit : — — — — — — TRGS1 TRGS0 Initial value : R/W : — — — — — — The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start factor. ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Page 613: Module Stop Control Register (Mstpcr)
Bit n PMR0n Description P0n/ANn functions as a general-purpose input port (Initial value) P0n/ANn functions as an analog input channel (n = 7 to 0) 26.2.7 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8...
Page 614: Interface To Bus Master
26.3 Interface to Bus Master ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 615: Operation
26.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. 26.4.1 Software-Triggered A/D Conversion A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Conversion can be software-triggered on any of the 12 channels provided by analog input pins AN0 to ANB.
Page 616: Hardware- Or External-Triggered A/D Conversion
26.4.2 Hardware- or External-Triggered A/D Conversion The system contains the hardware trigger function that allows to turn on A/D conversion at a specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the $'75* incoming external trigger ( ).
Page 617: Interrupt Sources
26.5 Interrupt Sources When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end interrupt can be enabled or disabled by ADIE bit in ADCSR. Figure 26.4 shows the block diagram of A/D conversion end interrupt. A/D control/status register (ADCSR) SEND HEND...
Page 618: Section 27 Address Trap Controller (Atc)
Section 27 Address Trap Controller (ATC) 27.1 Overview The address trap controller (ATC) is capable of generating interrupt by setting an address to trap, when the address set appears during bus cycle. 27.1.1 Features Address to trap can be set independently at three points. 27.1.2 Block Diagram Figure 27.1 shows a block diagram of the address trap controller.
Page 619: Register Configuration
27.1.3 Register Configuration Table 27.1 Register List Name Abbrev. Initial Value Address * Address trap control register ATCR H'F8 H'FFB9 Trap address register 0 TAR0 H'F00000 H'FFB0 to H'FFB2 Trap address register 1 TAR1 H'F00000 H'FFB3 to H'FFB5 Trap address register 2 TAR2 H'F00000 H'FFB6 to H'FFB8...
Page 620: Trap Address Register 2 To 0 (Tar2 To Tar0)
Bit 1: Trap Control 1 (TRC1) Sets ON/OFF operation of the address trap function 1. Bit 1 TRC1 Description Address trap function 1 disabled (Initial value) Address trap function 1 enabled Bit 0: Trap Control 0 (TRC0) Sets ON/OFF operation of the address trap function 0. Bit 0 TRC0 Description...
Page 621 TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16) TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8) TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1) If the value installed in this register and internal address buses A23 to A1 match as a result of comparison, an interruption occurs.
Page 622: Precautions In Usage
27.3 Precautions in Usage Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the setting up of the address trap. If the instruction to trap immediately follows the branch instruction or the conditional branch instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the branch.
Page 623 (2) Figure 27.3 shows the operation when the instruction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. The address to be stacked is 0268. Start of exception Data read...
Page 624: Enable
27.3.2 Enable The address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (TRCR) to 1. 029C BSET #0, @TRCR * 029E MOV.W R0, R1 After executing the MOV instruction, 02A0 MOV.B R1L, R3H the address trap interrupt does not...
Page 625 (2) When the condition is not satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction and prefetching the next instruction.
Page 626 (3) When condition is not satisfied by Bcc instruction (16-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction (if the trap address instruction is that of 2 states or more.
Page 627 (4) When the condition is not satisfied by Bcc instruction (Trap address at branch) When the trap address is at the branch of the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more.
Page 628: Bsr Instruction
27.3.4 BSR Instruction (1) BSR Instruction (8-bit displacement) When the trap address is the next instruction to the BSR instruction and the addressing mode is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C2. Stack Start of instruc-...
Page 629: Jsr Instruction
27.3.5 JSR Instruction (1) JSR Instruction (Register indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C8. Stack Start of instruc-...
Page 630: Jmp Instruction
27.3.6 JMP Instruction (1) JMP Instruction (Register indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02AA. Data Start of instruc-...
Page 631: Rts Instruction
27.3.7 RTS Instruction When the trap address is the next instruction to the RTS instruction, transition is made to the address trap interrupt after reading the CCR and PC from the stack and prefetching the instruction at the return location. The address to be stacked is 0298. Internal Stack Start of...
Page 632 (2) SLEEP Instruction 2 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling.
Page 633 (4) SLEEP Instruction 4 (Standby or Watch Mode Setting) When the trap address is the SLEEP instruction and the instruction immediately preceding the SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this puts in the standby (watch) mode after execution of the SLEEP instruction.
Page 634: Competing Interrupt
(5) SLEEP Instruction 5 (Standby or Watch Mode Setting) When the trap address is the next instruction to the SLEEP instruction, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading.
Page 635 0296 MOV.B R2L, @Port 029A 029C Set one of these to the 029E trap address 02A0 02A2 02A4 Start of general interrupt processing Data Data instruc- instruc- instruc- instruc- tion tion tion tion write read Range of start of ATC pre-fetch pre-fetch pre-fetch...
Page 636 (2) In case of NMI When the NMI interruption request is made at the timing in (1) (A) against the ATC interrupt request, the interrupt appears to take place in NMI at the timing earlier than usual, because higher priority is assigned to the NMI interrupt processing. The ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing.
Page 637 Figure 27.22 Competing Interrupt (In Case of NMI) Rev. 2.0, 11/00, page 610 of 1037...
Page 638: Section 28 Servo Circuits
Section 28 Servo Circuits 28.1 Overview 28.1.1 Functions Servo circuits for a video cassette recorder are included on-chip. The functions of the servo circuits can be divided into four groups, as listed in table 28.1. Table 28.1 Servo Circuit Functions Group Function Description...
Page 639: Block Diagram
28.1.2 Block Diagram Figure 28.1 shows a block diagram of the servo circuits. Rev. 2.0, 11/00, page 612 of 1037...
Page 640 PPG0 to 7/ PPG0 to 7/ (P70 to 77) (P70 to 77) PR0 to 7/ PR0 to 7/ (P60 to 67) (P60 to 67) EXTTRG/(P80) Csync 4-head Sync COMP(PS2) System special C.ROTARY(PS0) detector clock playback H.Amp SW(PS1) controller REC:ON Additional Capstan Drum system V pulse...
Page 641: Servo Port
28.2 Servo Port 28.2.1 Overview This LSI is equipped with seventeen pins dedicated to servo module and twenty-five dual- purpose pins used also for general-purpose port. It has also built-in input amplifier to amplify CTL signals, CTL output amplifier, CTL Schmitt comparator, and CFG zero cross type comparator.
Page 642 (2) CFG Input Circuit The CFG input pin has built-in an amplifier and a zero cross type comparator. Figure 28.3 shows the input circuit of CFG. P250 VREF CFGCOMP M250 CFGCOMP VREF RES+ModuleSTOP Figure 28.3 CFG Input Circuit Rev. 2.0, 11/00, page 615 of 1037...
Page 643 (3) CTL Input Circuit The CTL input pin has built-in an amplifier. Figure 28.4 shows the input circuit of CTL. AMPON AMPSHORT (PB-CTL) (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 PB-CTL(+) PB-CTL(-) CTL( CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i) Figure 28.4 CTL Input Circuit Rev.
Page 644: Pin Configuration
28.2.3 Pin Configuration Table 28.2 shows the pin configuration of the servo section. P6n, P7n, P80 to P38, and PS1 to PS4 are general-purpose ports. As for P6, P7, and P8, see section 10, I/O Port. Table 28.2 Pin Configuration Name Abbrev.
Page 645: Register Configuration
28.2.4 Register Configuration Table 28.3 shows the register configuration of the servo port section. Table 28.3 Register Configuration Name Abbrev. Size Initial Value Address Servo port mode register SPMR Byte H'40 H'FD0A0 Servo control register SPCR Byte H'E0 H'FD0A1 Servo data register SPDR Byte H'E0...
Page 646 Bit 5: CFG Input System Switching Bit (CFGCOMP) Selects whether the CFG input signal system is set to the zero cross type comparator system or digital signal input system. Bit 5 CFGCOMP Description CFG signal input system is set to the zero cross type comparator system (Initial value) CFG signal input system is set to the digital signal input system Bit 4: EXCTL Pin Switching Bit (EXCTLON)
Page 647 Bit 1: H.Amp SW Pin Switching Bit (H.Amp.SW) Selects whether the H.Amp SW/PS1 pin is used as the H.Amp SW output pin or PS1 (general- purpose I/O pin). Bit 1 H.Amp.SW Description H.Amp SW/PS1 pin functions as H.Amp SW output pin (Initial value) H.Amp SW/PS1 pin functions as PS1 I/O pin Bit 0: C.Rotary Pin Switching Bit (C.Rot)
Page 648 (3) Servo Data Register (SPDR) Bit : — — — SPDR4 SPDR3 SPDR2 SPDR1 SPDR0 Initial value : R/W : — — — Stores the data of each pin (PS4 to PS0) when the servo port/general-purpose dual-purpose pin is used as general-purpose port. If the port is accessed for read when SPCR is 1 (output), the SPDRn value is read directly.
Page 649 (4) Servo Monitor Control Register (SVMCR) Bit : — — SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 Initial value : R/W : — — Selects the monitor signal output to the SV1 and SV2 pins when the P82/SV1 pin is used as the SV1 monitor output pin or when the P83/SV2 pin is used as the SV2 monitor output pin.
Page 650 (5) CTL Gain Control Register (CTLGR) Bit : — — CTLE/ CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0 Initial value : — — R/W : Sets the CTLFB switch in the CTL amplifier circuit to on/off and CTL amplifier gain. CTLGR is an 8-bit read/write register. Bits 7 and 6 are reserved. No write in it is valid. If read is attempted, an undetermined value is read out.
Page 651 Bits 3 to 0: CTL Amplifier Gain Setting Bits (CTLGR3 to 0) Set the output gain of the CTL amplifier. Bit 3 Bit 2 Bit 1 Bit 0 CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL Output Gain 34.0 dB (Initial value) 36.5 dB 39.0 dB 41.5 dB 44.0 dB...
Page 652: Dfg/Dpg Input Signals
28.2.6 DFG/DPG Input Signals DFG and DPG signals allow either separate or overlapped input. If the latter was selected (DPGSW = 1), take care in the input levels of DFG and DPG. Figure 28.5 shows DFG/DPG input signals. DPG Schmitt level 3.45/3.55 DFG Schmitt level 1.85/1.95...
Page 653: Reference Signal Generators
28.3 Reference Signal Generators 28.3.1 Overview The reference signal generators consist of REF30 signal generator and CREF signal generator, and they create the reference signals (REF30 and CREF signals) used in phase comparison, etc. The REF30 signal is used to control the phase of the drum and capstan. The CREF signal is used if the reference signal to control the phase of the capstan cannot be shared with the REF30 signal in REC mode.
Page 654 Figure 28.6 REF30 Signal Generator Rev. 2.0, 11/00, page 627 of 1037...
Page 655: Register Configuration
PB(ASM) Counter clear DVCFG2 Counter (16 bit) Clear Match Edge Comparator (16 bit) Toggle CREF detection Reference period register 2 (16 bit) Reference period buffer 2 (16 bit) Dummy read Internal bus s = fosc/2 Figure 28.7 Block Diagram of CREF Signal Generator 28.3.3 Register Configuration Table 28.4 shows the register configuration of the reference signal generators.
Page 656: Register Descriptions
28.3.4 Register Descriptions (1) Reference Period Mode Register (RFM) Bit : OD/EV Initial value : R/W : RFM is an 8-bit write-only register which determines the operational state of the reference signal generators. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop.
Page 657 Bit 5: Manual Selection Bit (CVS) Selects whether the REF30 signals are generated in sync with VD or operated free-run in manual mode (VNA = 0). (No selection is reflected in PB mode, except in TBC mode.) Bit 5 Description Sync with VD (Initial value) Free-run operation...
Page 658 Bit 1: Video FF Counter Set (VST) Selects whether the REF30 counter register value is set on or off by the Video FF signal when the drum phase is in FIX on in PB mode. Bit 1 Description Counter set off by Video FF signal (Initial value) Counter set on by Video FF signal Bit 0: Video FF Edge Selection Bit (VEG)
Page 659 (2) Reference Period Register 1 (RFD) Bit : REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Initial value : R/W : The reference period register 1 (RFD) is a buffer register which generates the reference signals for playback (REF30), VD compensation for recording and the reference signals for free- running.
Page 660 (3) Reference Period Register 2 (CRF) Bit : CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 Initial value : R/W : The reference period register 2 (CRF) is a 16-bit write-only buffer register which generates the reference signals to control the capstan phase (CREF).
Page 661 (5) Reference Period Mode Register 2 (RFM2) Bit : (TBC) — — — — — — Initial value : (R/W) * — — — — — — R/W : Note:* Writable only in the H8S/2194C Series. RFM2 is an 8-bit read/write register which determines the operational state of the reference signal generators.
Page 662: Description Of Operation
28.3.5 Description of Operation (1) Operation of REF30 Signal Generators The REF30 signal generators generate the reference signals required to control the phase of the drum and capstan. To generate REF30 signals, set the half-period value to the reference period register 1 (RFD) corresponding to the 50% duty cycle.
Page 663 (3) Timing of the REF30 Signal Generation Figures 28.8, 28.9, 28.10, 28.11 and 28.12 show the timing of the generation of REF30 and REF30P signals. Counter set Counter set Counter set Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) REF30...
Page 664 Field signal Selected VD (OD/EV=0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (clear signal mask) About 75% REF30 REF30P Drum phase counter Sampling Sampling Sampling Figure 28.9 Generation of Reference Signal in Record Mode (Normal Operation)
Page 665 Field signal Drop-out of V Selected VD (OD/EV=0) Cleared Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period About 75% About 75% About 75% Counter mask Masking period (clear signal mask) About...
Page 666 Field signal Dislocation of V Selected VD (OD/EV=0) Cleared Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period About 75% About 75% Counter mask Masking period (clear signal mask) About 75% About 75% REF30...
Page 667 External sync signal Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Reset REF30 REF30P Figure 28.12 Generation of REF30 Signal by External Sync Signal (4) CREF Signal Generator The CREF signal generator generates a CREF signal which is the reference signal to control the phase of the capstan.
Page 668 (5) Timing Chart of the CREF Signal Generation Figures 28.13, 28.14 and 28.15 show the generation of the CREF signal. Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter Toggle signal CREF Figure 28.13 Generation of CREF Signal Rev.
Page 669 Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB Toggle signal Time period when CRF is set CREF PB(ASM) Figure 28.14 CREF Signal when PB is Switched to REC (when CRD Bit = 0) Rev. 2.0, 11/00, page 642 of 1037...
Page 670 Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB DVCFG2 Toggle signal Time period when CRF is set CREF PB(ASM) Figure 28.15 CREF Signal when PB is Switched to REC (when CRD Bit = 1) Rev. 2.0, 11/00, page 643 of 1037...
Page 671 Figures 28.16 and 28.17 show REF30 (REF30P) when PB is switched to REC. REC(ASM) Field signal VD (except in PB) Selected VD * (OD/EV=0) REC/PB Value set in reference Cleared Cleared Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask...
Page 672 REC(ASM) Field signal VD (except in PB) Selected VD (OD/EV=0) REC/PB Value set in reference Cleared Cleared period register 1 (RFD) Cleared Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Masking Counter mask period (Clear signal mask) About Cleared REF30...
Page 673 Figures 28.18, 28.19, 28.20 and 28.21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1). REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask...
Page 674 REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) REF30 REF30P FDS bit = "1" Figure 28.19 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (when VD Signal is Not Detected) (2) Rev.
Page 675 REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) Max. 25% REF30 REF30P FDS bit = "1" Figure 28.20 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (3) Rev.
Page 676 REC(ASM) REC/PB VD (except in PB) Value set in reference Cleared Cleared period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Masking Toggle mask period Counter mask Masking period (Clear signal mask) Max. 25% REF30 REF30P FDS bit = "1" Figure 28.21 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (4) Rev.
Page 677: Hsw (Head-Switch) Timing Generator
28.4 HSW (Head-switch) Timing Generator 28.4.1 Overview The HSW timing generator consists of one 5-bit counter and one 16-bit counter, matching circuit, and two 31-bit 10-stage FIFOs. The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the timing to reset the 16-bit timer for each field.
Page 678 Figure 28.22 Composition of the HSW Timing Generator Rev. 2.0, 11/00, page 651 of 1037...
Page 679: Composition
28.4.3 Composition The HSW timing generator is composed of the elements shown in table 28.5. Table 28.5 Composition of the HSW Timing Generator Element Function HSW mode register 1 (HSM1) Confirmation/determination of this circuits' operating status HSW mode register 2 (HSM2) Confirmation/determination of this circuits' operating status HSW loop stage number setting register...
Page 680: Register Configuration
28.4.4 Register Configuration Table 28.6 shows the register configuration of the HSW timing generator. Table 28.6 Register Configuration Name Abbrev. Size Initial Value Address HSW mode register 1 HSM1 Byte H'30 H'FD060 HSW mode register 2 HSM2 Byte H'00 H'FD061 HSW loop stage number setting HSLP Byte...
Page 681 Bit 7: FIFO2 Full Flag (FLB) When the FLB bit is 1, it indicates that the timing pattern data and the output pattern data of FIFO2 are full. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost.
Page 682 Bit 3: FIFO2 Overwrite Flag (OVWB) If a write is attempted when the timing pattern data and the output pattern data of FIFO2 are full (FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is set to 1, and the write data is lost.
Page 683 Bit 0: FIFO1 Pointer Clear (CLRA) Clears the FIFO1 write position pointer. After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect. Bit 0 CLRA Description Normal operation (Initial value) Clears the FIFO1 pointer Rev.
Page 684 (2) HSW Mode Register 2 (HSM2) Bit : FGR20FF ISEL1 SOFG VFF/NFF Initial value : R/W : HSM2 is a register which confirms and determines the operational state of the HSW timing generator. HSM2 is an 8-bit register. Bits 6 and 1 are read-only bits, and write is disabled. Bit 0 is a write- only bit, and if a read is attempted, an undetermined value is read out.
Page 685 Bit 4: DFG Edge Selection Bit (EDG) Selects the edge by which to count DFG. Bit 4 Description Counts by the rising edge of DFG (Initial value) Counts by the falling edge of DFG Bit 3: Interrupt Selection Bit (ISEL1) Selects the factor which causes an interrupt.
Page 686 Bit 0: Output Switching Bit Between VideoFF and NarrowFF (VFF/NFF) Switches the signal output to the VideoFF pin. Bit 0 VFF/NFF Description VideoFF output (Initial value) NarrowFF output Rev. 2.0, 11/00, page 659 of 1037...
Page 687 (3) HSW Loop Stage Number Setting Register (HSLP) Bit : LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0 Initial value : R/W : Note: * Undetermined HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is valid if bit 5 (LOP) of HSM2 is 1.
Page 688 Bits 7 to 4: FIFO2 Stage Number Setting Bits (LOB3 to LOB0) Set the number of FIFO2's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5 Bit 7 Bit 6 Bit 5...
Page 689 Bits 3 to 0: FIFO1 Stage Number Setting Bits (LOA3 to LOA0) Set the number of FIFO1's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5 Bit 3 Bit 2 Bit 1...
Page 690 (4) FIFO Output Pattern Register 1 (FPDRA) Bit : ADTRGA STRIGA NarrowFFA VFFA AFFA VpulseA MlevelA — Initial value : — R/W : Bit : PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0 Initial value : R/W : Note: * Undetermined FPDRA is a buffer register for the output pattern register of FIFO1.
Page 691 Bit 8: MlevelA Bit (MlevelA) Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bits 7 to 0: PPG Output Signal A Bits (PPGA7 to PPGA0) Used for timing control output of port 7 (PPG). (5) FIFO Output Pattern Register 2 (FPDRB) Bit : —...
Page 692 Bit 10: AudioFFB Bit (AFFB) Controls the Audio Head. Bit 9: VpulseB Bit (VpulseB) Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information. Bit 8: MlevelB Bit (MlevelB) Used for generating an additional V signal. See section 28.12, Additional V Signal Generator, for more information.
Page 693 (7) FIFO Timing Pattern Register 2 (FTPRB) Bit : FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0 Initial value : R/W : Note: * Undetermined FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in FTPRB is written at the same time to the position pointed by the buffer pointer of FIFO2 together with the buffer data of FPDRB.
Page 694 Bit 6: DFG Counter Clear Bit (CCLR) Enforces clearing of the 5-bit counter which counts DFG by software. Writing 1 returns 0 immediately. Writing 0 causes no effect on operation. Bit 6 CCLR Description Normal operation (Initial value) Clears the 5-bit DFG counter Bit 5: 16-bit Timer Counter Clock Source Selection Bit (CKSL) Selects the clock source of the 16-bit timer counter.
Page 695 (10) FIFO Timer Capture Register (FTCTR) Bit : FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0 Initial value : R/W : FTCTR is a register to display the count of the 16-bit timer counter. FTCTR is a 16-bit read-only register.
Page 696: Description Of Operation
28.4.6 Description of Operation (a) 5-bit DFG counter The 5-bit DFG counter takes counts by the edges of DFG selected by the EDG bit of HSW mode register 2. The 5-bit DFG counter is cleared by the DPG's rise or when 1 was written in the CCLR bit of DFG reference register 1.
Page 697 • Loop Mode In loop mode, the output pattern cycles repeatedly from stage 0 through the final stage selected in the HSW loop number setting register. As in single mode, the output pattern data is output each time the timing data matches. In loop mode, the FIFO data is retained.
Page 698 Figure 28.23 Example of Timing Waveform of HSW (when DFG is 12 Shots) Rev. 2.0, 11/00, page 671 of 1037...
Page 699 Internal bus FPDRA FPDRB FTPRA FTPRB FIFO1 FIFO2 Output select buffer Output select buffer Comparator Timer counter Output pattern data Figure 28.24 Example of Operation of the HSW Timing Generator Rev. 2.0, 11/00, page 672 of 1037...
Page 700 (1) Example of operation in single mode (20 stages of FIFO used) (a) Set to single mode (LOP = 0) (b) Write the output pattern data (PA0) to FPDRA. (c) Write the output timing (t ) to FTPRA. tA1 is written in FIFO1 together with PA0. This initializes the output pattern data to PA0.
Page 701 After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is required, however, because matching of t is not detected until data is written in FIFO2.
Page 702: Interrupt
28.4.7 Interrupt The HSW timing generator generates an interrupt under the following conditions. (1) IRRHSW1 occurred when pattern data was written (OVWA, OVWB = 1) and FIFO was full (FULL). (2) IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1. (3) IRRHSW1 occurred when the values of the 16-bit timer counter and 16-bit timing pattern register matched.
Page 703: Cautions
28.4.8 Cautions (1) When both the 5-bit DFG counter and 16-bit timer counter are operating, the latter is not cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit timer counter, and periodical detection of matching by the 16-bit timer counter. In such a case, the period of the output from the HSW timing generator is independent from DPG or DFG.
Page 704: Four-Head High-Speed Switching Circuit For Special Playback
28.5 Four-head High-speed Switching Circuit for Special Playback 28.5.1 Overview This four-head high-speed switching circuit generates a color rotary signal (C.Rotary) and head- amplifier switching signal (H.Amp SW) for use in four-head special playback. A pre-amplifier output comparison result signal is input from the COMP pin. The signal output at the C.Rotary pin is a Chroma signal processing control signal.
Page 705: Pin Configuration
28.5.3 Pin Configuration Table 28.7 summarizes the pin configuration of the high-speed switching circuit used in four- head special playback. They can also be used as I/O ports when not in use. See section 28.2, Servo Port. Table 28.7 Pin Configuration Name Abbrev.
Page 706 (2) Special Playback Control Register (CHCR) Bit : HSWPOL SIG3 SIG2 SIG1 SIG0 Initial value : R/W : The special playback control register (CHCR) is an 8-bit write-only register. It cannot be read. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop.
Page 707 Bit 4: H.Amp SW Synchronization Control Bit (HAH) Synchronizes the H.Amp SW signal with the OSCH signal. Bit 4 Description Synchronous (Initial value) Asynchronous Bits 3 to 0: Signal Control Bits (SIG3 to SIG0) These bits, combined with the state of the COMP input pin, control the outputs at the C.Rotary and H.Amp SW pins.
Page 708: Drum Speed Error Detector
28.6 Drum Speed Error Detector 28.6.1 Overview Drum speed error control operates so as to hold the drum at a constant revolution speed by measuring the period of the DFG signal. A digital counter detects the speed deviation from a preset value.
Page 709 Figure 28.27 Block Diagram Of The Drum Speed Error Detector Rev. 2.0, 11/00, page 682 of 1037...
Page 710: Register Configuration
28.6.3 Register Configuration Table 28.9 shows the register configuration of the drum speed error detector. Table 28.9 Register Configuration Name Abbrev. Size Initial Value Address Specified DFG speed DFPR Word H'0000 H'FD030 preset data register DFG speed error data DFER Word H'0000 H'FD032...
Page 711: Register Descriptions
28.6.4 Register Descriptions (1) Specified DFG Speed Preset Data Register (DFPR) Bit : Initial value : R/W : The specified DFG speed preset data is set in DFPR. When the data is written, a 16-bit preset data is sent to the preset circuit. The preset data is referenced to H'8000*, and can be calculated from the following equation.
Page 712 (2) DFG Speed Error Data Register (DFER) Bit : Initial value : R/W : R * /W R * /W R * /W R * /W R * W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W...
Page 713 (4) DFG Lock LOWER Data Register (DFRLDR) Bit : Initial value : R/W : DFRLDR is a register used to set the lock range on the LOWER side when drum speed lock is detected, and to set the limit value on LOWER side when the limiter function is in use. Set a signed data to DFRLDR (bit 15 is a sign-setting bit).
Page 714 Bits 7 and 6: Clock Source Selection Bits (DFCS1, DFCS0) DFCS1 and DFCS0 select the clock to be supplied to the counter. (φs = fosc/2) Bit 7 Bit 6 DFCS1 DFCS0 Description φs (Initial value) φs/2 φs/4 φs/8 Bit 5: Counter Overflow Flag (DFOVF) The DFOVF flag indicates the overflow of the 16-bit counter.
Page 715 Bit 2: Drum Phase System Filter Computation Automatic Start Bit (DPCNT) Sets on the filter computation of the phase system if an underflow occurred in the drum lock counter. Bit 2 DPCNT Description Does not perform the filter computation by detection of the drum lock (Initial value) Sets on the filter computation of the phase system when drum lock is detected Bits 1 and 0: Drum Lock Counter Setting Bits (DFRCS1, DFRCS0) Set the number of times where drum lock has been determined (DFG has been detected in the...
Page 716: Description Of Operation
28.6.5 Description of Operation The drum speed error detector detects the speed error based on the reference value set in the DFG specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter by the NCDFG signal, and counts down by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of the NCDFG signal.
Page 717 (d) Interrupt request IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection counter. IRRDRM2 is generated by detection of lock (after the detection of the number of times of setting). NCDFG signal Error data latch signal (DFG ) Preset data load...
Page 718: Correction In Trick Play Mode
28.6.6 Correction in Trick Play Mode In trick play mode, the tape speed changes relative to the video head. This change alters the horizontal sync signal (f ), causing skew. To correct the skew, the drum motor speed must be shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync frequency.
Page 719: Drum Phase Error Detector
28.7 Drum Phase Error Detector 28.7.1 Overview Drum phase control must start operating after the drum motor is brought to the correct revolution speed by the speed control system. Drum phase control works as follows in record and playback. Record: Phase is controlled so that the vertical blanking intervals of the recorded video signal will line up along the bottom edge of the tape.
Page 720 Figure 28.29 Block Diagram of Drum Phase Error Detector Rev. 2.0, 11/00, page 693 of 1037...
Page 721: Register Configuration
28.7.3 Register Configuration Table 28.10 shows the register configuration of the drum phase error detector. Table 28.10 Register Configuration Name Abbrev. Size Initial Value Address Drum phase preset data DPPR1 Byte H'F0 H'FD03C register 1 Drum phase preset data DPPR2 Word H'0000 H'FD03A...
Page 722: Register Descriptions
28.7.4 Register Descriptions (1) Drum Phase Preset Data Registers (DPPR1, DPPR2) DPPR1 Bit : — — — — Initial value : — — — — R/W : DPPR2 Bit : Initial value : R/W : The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The 20 bits are weighted as follows.
Page 723 (2) Drum Phase Error Data Registers (DPER1, DPER2) DPER1 Bit : — — — — Initial value : — — — — R * /W R * /W R * /W R * /W R/W : DPER2 Bit : Initial value : R/W : R * /W R * /W...
Page 724 (3) Drum Phase Error Detection Control Register (DPGCR) Bit : DPCS1 DPCS0 DPOVF HSWES — — — Initial value : R/(W) * — — — R/W : Note: * Only 0 can be written DPGCR controls the operation of drum phase error detection. DPGCR is an 8-bit readable/writable register.
Page 725: Description Of Operation
Bit 4: Error Data Latch Signal Selection Bit (N/V) Selects the latch signal of error data. Bit 4 Description HSW (VideoFF) signal (Initial value) NHSW (NarrowFF) signal Bit 3: Edge Selection Bit (HSWES) Selects the edge of the error data latch signal (HSW or NHSW). Bit 3 HSWES Description...
Page 726 REF30P HSW (NHSW) * Preset Preset Counter Latch Latch Preset value Preset value Note: * Edge selectable Figure 28.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected) Reset Reset REF30P HSW (NHSW) * Preset Preset Counter Latch Latch Preset value Preset value Note: * Edge selectable...
Page 727: Phase Comparison
28.7.6 Phase Comparison The phase comparison circuit takes measures of the difference of time between the reference signal and the comparing signal with a digital counter. The REF30 signal is used for the reference signal, and the HSW signal (VideoFF) or HHSW signal (NarrowFF) from the HSW timing generator is used for the comparing signal.
Page 728: Capstan Speed Error Detector
28.8 Capstan Speed Error Detector 28.8.1 Overview Capstan speed control operates so as to hold the capstan motor at a constant revolution speed, by measuring the period of the CFG signal. A digital counter detects the speed deviation from a preset value.
Page 729 Figure 28.32 Block Diagram of Capstan Speed Error Detector Rev. 2.0, 11/00, page 702 of 1037...
Page 730: Register Configuration
28.8.3 Register Configuration Table 28.11 shows the register configuration of the capstan speed error detector. Table 28.11 Register Configuration Name Abbrev. Size Initial Value Address CFG speed preset data CFPR Word H'0000 H'FD050 register CFG speed error data CFER Word H'0000 H'FD052 register...
Page 731: Register Descriptions
28.8.4 Register Descriptions (1) CFG Speed Preset Data Register (CFPR) Bit : Initial value : R/W : The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is referenced to H'8000*, and can be calculated from the following equation. φs/n CFG speed preset data =H'8000 −...
Page 732 (2) CFG Speed Error Data Register (CFER) Bit : Initial value : R/W : R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W...
Page 733 (4) CFG Lock LOWER Data Register (CFRLDR) Bit : Initial value : R/W : CFRLDR is a register used to set the lock range on the LOWER side when capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is in use. When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by the CFRCS1 and CFRCS0 bits of the CFVCR register counts down.
Page 734 Bit 5: Counter Overflow Flag (CFOVF) The CFOVF flag indicates overflow of the 16-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified.
Page 735: Description Of Operation
Bits 1 and 0: Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0) Sets the number of times where drum lock has been determined (DVCFG has been detected in the range set by the lock range data register). It sets the capstan lock flag if it detected the set number of times of occurrence of capstan lock.
Page 736 (b) Lock detection If error data was detected within the lock range set in the lock data register, the capstan lock flag (CF-R/UNR) is set by the number of the times of occurrence of locking set by the CFRCS1 and CFRCS0 bits, and an interrupt is requested (IRRCAP2) at the same time. The number of the occurrence of locking (once to 4 times) can be specified when setting the flag.
Page 737: Capstan Phase Error Detector
28.9 Capstan Phase Error Detector 28.9.1 Overview The capstan phase control system is required to start operation after the capstan motor has arrived at the specified speed under the control of the speed control system. The capstan phase control system operates in the following way in record/playback mode. In record mode: Controls the tape running so that it may run at a specified speed together with the speed control system.
Page 738 Figure 28.34 Block Diagram of Capstan Phase Error Detector Rev. 2.0, 11/00, page 711 of 1037...
Page 739: Register Configuration
28.9.3 Register Configuration Table 28.12 shows the register configuration of the capstan phase error detector. Table 28.12 Register Configuration Name Abbrev. Size Initial Value Address* Capstan phase preset CPPR1 Byte H'F0 H'FD05C data register 1 Capstan phase preset CPPR2 Word H'0000 H'FD05A data register 2...
Page 740: Register Descriptions
28.9.4 Register Descriptions (1) Capstan Phase Preset Data Registers (CPPR1, CPPR2) CPPR1 Bit : — — — — Initial value : — — — — R/W : CPPR2 Bit : Initial value : R/W : The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The 20 bits are weighted as follows.
Page 741 (2) Capstan Phase Error Data Registers (CPER1, CPER2) Bit : — — — — Initial value : R * /W R * /W R * /W R * /W R/W : — — — — Bit : Initial value : R/W : R * /W R * /W...
Page 742 (3) Capstan Phase Error Detection Control Register (CPGCR) Bit : CPCS1 CPCS0 CPOVF CR/RF SELCFG2 — — — Initial value : R/(W) * — — — R/W : Note: * Only 0 can be written CPGCR controls the operation of capstan phase error detection. CPGCR is an 8-bit readable/writable register.
Page 743: Description Of Operation
Bit 4: Preset Signal Selection Bit (CR/RF) Selects the preset signal. Bit 4 CR/RF Description Presets REF30P signal (Initial value) Presets CREF signal Bit 3: Preset and Latch Signal Selection Bit (SELCFG2) Selects the counter preset signal and the error data latch signal data in PB (ASM) mode. Bit 3 SELCFG2 Description...
Page 744 (b) Interrupt request IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the overflow of the error detection counter. CAPREF30 PB-CTL DVCTL DVCFG2 Preset Preset Counter Latch Latch Preset value Figure 28.35 Capstan Phase Control in Playback Mode REF30P CREF DVCFG2...
Page 745: X-Value And Tracking Adjustment Circuit
28.10 X-Value and Tracking Adjustment Circuit 28.10.1 Overview To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of the reference signal (internal reference signal (REF30) or external reference signal (EXCAP)) during playback. Because of manufacturing tolerances, the physical distance between the video head and control head (the X-value: 79.244 mm) may vary from set to set, so when a tape that was recorded on a different set is played back, the phase of the reference signal may...
Page 746 Figure 28.37 Block Diagram of X-Value Adjustment Circuit Rev. 2.0, 11/00, page 719 of 1037...
Page 747: Register Descriptions
28.10.3 Register Descriptions (1) Register Configuration Table 28.13 shows the register configuration of X-value adjustment and tracking adjustment circuits. Table 28.13 Register Configuration Name Abbrev. Size Initial Value Address* X-value and TRK-value XTCR Byte H'80 H'FD074 control register X-value data register Word H'F000 H'FD070...
Page 748 Bit 5: Capstan Phase Correction Auto/Manual Selection Bit (AT/ Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase control is controlled automatically or manually depending on the status of the ASM and REC/ bits of the CTL mode register. Bit 5 &...
Page 749 Bits 1 and 0: REF30P Division Ratio Selection Bits (DVREF1, DVREF0) Select the division value of REF30P. If it is read-accessed, the counter value is read out. (The selected division value is set by the UDF of the counter.) Bit 1 Bit 0 DVREF1 DVREF0...
Page 750: Digital Filters
28.11 Digital Filters 28.11.1 Overview The digital filters required in servo control make extensive use of multiply-accumulate operations on signed integers (error data) and coefficients. A filter computation circuit (digital filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to improve processing efficiency.
Page 751: Block Diagram
28.11.2 Block Diagram Error latch signal Accumulator Accumulation Error check controller Accumulation sequence circuit Start Data LA (16 bits), Buffer/ shifter lower accumulator register select & Sign UA (32 bits), controller A, B, G, etc. upper accumulator Write-only MD (32 bits), multiplied data Read-only Buffer circuit...
Page 752 Figure 28.39 Digital Filter Representation Rev. 2.0, 11/00, page 725 of 1037...
Page 753: 28.11.3 Arithmetic Buffer
28.11.3 Arithmetic Buffer This buffer stores computational data used in the digital filters. See table 28.14. Write access is limited to the gain and coefficient data (Z ). Other data is used by hardware. None of the data can be read. Table 28.14 Arithmetic Buffer Register Configuration Buffer Data Length 16 bits...
Page 754: Register Configuration
28.11.4 Register Configuration Table 28.15 shows the register configuration of the digital filter computation circuit. Table 28.15 Register Configuration Name Abbrev. Size Initial Value Address Capstan phase gain CGKp Word Undetermined H'FD010 constant Capstan speed gain CGKs Word Undetermined H'FD012 constant Capstan phase coefficient A Word...
Page 755: Register Descriptions
28.11.5 Register Descriptions (1) Gain Constants (DGKp, DGKs, CGKp, CGKs) Bit : Initial value : R/W : Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. They cannot be read. They can be accessed by word access only. Accumulation gain can be set to gain 1 value as the maximum value.
Page 756 (3) Offsets (DOfp, DOfs, COfp, COfs) Bit : Initial value : R/W : Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set the offset level of digital filter output. They cannot be read. They can be accessed by word access only. Byte access gives unassured results. If read is attempted, an undetermined value is read out.
Page 757 (5) Drum System Digital Filter Control Register (DFIC) Bit : — DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 Initial value : R/(W) * R/(W) — R/W : Note: * Only 0 can be written DFIC is an 8-bit readable/writable register that controls the status of the drum system digital filter and operating mode.
Page 758 Bit 4: Drum Phase System Z Initialization Bit (DZPON) Reflects the DZp value on Z of the phase system when computation processing of the drum phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp.
Page 759 (6) Capstan System Digital Filter Control Register (CFIC) Bit : — DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 Initial value : R/(W) * — R/W : R/(W) Note: * Only 0 can be written CFIC is an 8-bit readable/writable register that controls the status of the capstan system digital filter and operating mode.
Page 760 Bit 4: Capstan Phase System Z Initialization Bit (CZPON) Reflects the CZp value on Z of the capstan phase system when computation processing of the phase system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZp.
Page 761 (7) Digital Filter Control Register (DFUCR) Bit : — — PTON CP/DP CFEPS DFEPS CFESS DFESS Initial value : — — R/W : DFUCR is an 8-bit readable/writable register which controls the operation of the digital filter. It accepts a byte-access only. If it was word-accessed, operation is not assured. Bits 7 and 6 are reserved.
Page 762 Bit 3: Capstan Phase System Error Data Transfer Bit (CFEPS) Transfers the capstan phase system error data to the digital filter when the data write is enforced. Bit 3 CFEPS Description Error data is transferred by DVCFG2 signal latching (Initial value) Error data is transferred when the data is written Bit 2: Drum Phase System Error Data Transfer Bit (DFEPS) Transfers the drum phase system error data to the digital filter when the data write is enforced.
Page 763: 28.11.6 Filter Characteristics
28.11.6 Filter Characteristics (1) Lag-Lead Filter A filter required for a servo loop is built in the hardware. This filter uses an IIR (Infinite Impulse Response) type digital filter (another type of the digital filter is FIR, i.e. Finite Impulse Response type). This digital filter circuit implements a lag-lead filter, as shown in figure 28.40.
Page 764 (2) Frequency Characteristics The computation circuit repeats computation of the function, which is obtained by s-z conversion according to bi-linear approximation of the transfer function on the s-plane. Figure 28.41 shows the frequency characteristics of the lag-lead filter. 20log(f1/f2) Frequency (Hz) Figure 28.41 Frequency Characteristics of the Lag-Lead Filter The pulse transfer function G(Z) is obtained by the bi-linear approximation of the transfer function G (S).
Page 765: 28.11.7 Operations In Case Of Transient Response
28.11.7 Operations in Case of Transient Response In case of transient response when the motor is activated, the digital filter computation circuit must prevent computation due to a large error. The convergence of the computations becomes slow and servo retraction becomes deteriorating if a large error is input to the filter circuit when it is performing repeated computations.
Page 766 Usn-1 DZs11 to 0 DZp11 to 0 CZs11 to 0 Delay initialization CZp11 to 0 register DAs15 to 0 DBs15 to 0 DAp15 to 0 DBp15 to 0 CAs15 to 0 CBs15 to 0 initiali- CAp15 to 0 CBp15 to 0 zation bit DZSON DZPON...
Page 767: Additional V Signal Generator
28.12 Additional V Signal Generator 28.12.1 Overview The circuit described in this section outputs an additional vertical sync signal to take the place of Vsync in special playback. It is activated at both edges of the HSW signal output by the head- switch timing generator.
Page 768: Pin Configuration
28.12.2 Pin Configuration Table 28.16 summarizes the pin configuration of the additional V signal. Table 28.16 Pin Configuration Name Abbrev. Function Additional V pulse pin Vpulse Output Output of additional V signal synchronized to VideoFF 28.12.3 Register Configuration Table 28.17 summarizes the register that controls the additional V signal. Table 28.17 Register Configuration Name Abbrev.
Page 769 Bit 4 HMSK Description OSCH is added in (Initial value) OSCH is not added in Bit 3: High Impedance Bit (HiZ) Set to 1 when the intermediate level is generated by an external circuit. Bit 3 Description Vpulse is a three-level output pin (Initial value) Vpulse is a three-state output pin (high, low, or high-impedance) Bits 2 to 0: Additional V Output Control Bit (CUT, VPON, POL)
Page 770: 28.12.5 Additional V Pulse Signal
28.12.5 Additional V Pulse Signal Figure 28.44 shows the additional V pulse signal. The Mlevel and Vpulse signals are generated by the head-switch timing generator. The OSCH signal is combined with these to produce equalizing pulses. The polarity can be selected by the POL bit in the additional V register (ADDVR).
Page 771 (a) Additional V pulses when sync signal is not detected With additional V pulses, the pulse signal (OSCH) detected by the sync detector is superimposed on the Vpulse and Mlevel signals generated by the head-switch timing generator. If there is a lot of noise in the input sync signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H pulse of the period set in HRTR and HPWR will be superimposed.
Page 772 HSW signal edge Mlevel signal Vpulse signal OSCH Additional V pulse VPON=1, CUT=0, POL=0 Figure 28.46 Additional V Pulse When Negative Polarity is Specified Rev. 2.0, 11/00, page 745 of 1037...
Page 773: Ctl Circuit
28.13 CTL Circuit 28.13.1 Overview The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits. The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records VISS, ASM, and VASS marks.
Page 774: Block Diagram
28.13.2 Block Diagram Figure 28.47 shows a block diagram of the CTL circuit. PB-CTL CTL mode IRRCTL Duty des- VISS detect FW/RV criminator VISS control circuit detector VISS write REF30X Bit pattern register Write control circuit Duty I/O flag Internal bus Schmitt amplifier REC-...
Page 775: Pin Configuration
28.13.3 Pin Configuration Table 28.18 summarizes the pin configuration of the CTL circuit. Table 28.18 Pin Configuration Name Abbrev. Function CTL (+) I/O pin CTL (+) CTL signal input/output CTL (–) I/O pin CTL (–) CTL signal input/output CTL Bias input pin CTL Bias Input CTL primary amplifier bias supply...
Page 776: Register Descriptions
28.13.5 Register Descriptions (1) CTL Control Register (CTCR) Bit : NT/PL FSLC FSLB FSLA LCTL UNCTL SLWM Initial value : R/W : The CTL control register (CTCR) controls PB-CTL rewrite and sets the slow mode. When a CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register (CTLGR) in the PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1.
Page 777 Bits 3: Clock Source Selection Bit (CCS) Selects clock source of CTL. Bit 3 Description φs (Initial value) φs/2 Bit 2: Long CTL Bit (LCTL) Sets the long CTL detection mode. Bit 2 LCTL Description Clock source (CCS) operates at the setting value (Initial value) Clock source (CCS) operates for further 8-division after operating at the setting value...
Page 778 (2) CTL Mode Register (CTLM) Bit : REC/PB FW/RV Initial value : R/W : The CTL mode register (CTLM) is an 8-bit readable/writable register that controls the operating state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
Page 779 CTL input PB-CTL Figure 28.48 Internal PB-CTL Signal in Forward and Reverse Bits 4 to 0: CTL Mode Selection Bits (MD4 to MD0) These bits select the detect, record, and rewrite modes for VISS, VASS, and ASM marks. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
Page 780 ! ! Mode Description • The duty I/O flag is set to 1 at the VISS detect point of write access to register (index CTLM detect) • The 1 pulses recognized by the duty discrimination circuit are counted in the VISS control circuit •...
Page 781 (3) REC-CTL Duty Data Register 1 (RCDR1) Bit : — — — — CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 Initial value : — — — — R/W : RCDR1 is a register that sets the REC-CTL rising timing. This setting is valid only for recording and rewriting, and is not used in detection.
Page 782 (4) REC-CTL Duty Data Register 2 (RCDR2) Bit : — — — — CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 Initial value : — — — — R/W : RCDR2 is a register that sets 1 pulse (short) falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Page 783 (5) REC-CTL Duty Data Register 3 (RCDR3) Bit : — — — — CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 Initial value : R/W : — — — — RCDR3 is a register that sets 1 pulse (long) and assemble mark falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Page 784 (6) REC-CTL Duty Data Register 4 (RCDR4) Bit : — — — — CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 Initial value : — — — — R/W : RCDR4 sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite mode.
Page 785 (7) REC-CTL Duty Data Register 5 (RCDR5) Bit : — — — — CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 Initial value : R/W : — — — — RCDR5 sets the timing of falling edge of the 0 pulse (long) of REC-CTL in record or rewrite mode.
Page 786 (8) Duty I/O Register (DI/O) Bit : VCTR2 VCTR1 VCTR0 — BPON DI/O Initial value : R/(W) * — R/W : Note: * Only 0 can be written. The duty I/O register is an 8-bit register that confirms and determines the operating status of the CTL circuit.
Page 787 Bit 3: Bit Pattern Detection ON/OFF Bit (BPON) Determines ON or OFF of bit pattern detection. Note: When writing 1 to the BPON bit, be sure to set appropriate data to RCDR2 to RCDR5 beforehand. Bit 3 BPON Description Bit pattern detection OFF (Initial value) Bit pattern detection ON Bit 2: Bit Pattern Detection Start Bit (BPS)
Page 788 VISS Detect Mode and VASS Detect Mode: The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is equal to or above 44% (a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is below 43% (a 1 pulse in the CTL signal).
Page 789 (9) Bit Pattern Register (BTPR) Bit : LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0 Initial value : R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : Note: * Write is prohibited when bit pattern detection is selected. The bit pattern register (BTPR) is an 8-bit shift register which detects and records the bit pattern of the CTL pulses.
Page 790: Operation
28.13.6 Operation (a) CTL circuit operation As shown in figure 28.49, the CTL discrimination/record circuit is composed of a 16-bit up/down counter and 12-bit registers (×5). In playback (PB) mode, the 16-bit up/down counter counts on a φs/4 clock when the PB-CTL pulse is high, and on a φs/5 clock when low.
Page 791 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle REF30P X-value Latch after Preset change X-value Capstan phase control ASM mode, PB mode : REF30X-PB-CTL REC mode : REF30P-DVCFG2...
Page 792 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle REF30P X-value after change X value Capstan phase control ASM mode, PB mode: REF30X-PB-CTL REF30X PB-CTL REC-CTL...
Page 793: 28.13.7 Ctl Input Section
28.13.7 CTL Input Section The CTL input section consists of an input amplifier whose gain can be controlled by register setting and a Schmitt amplifier. Figure 28.52 shows a block diagram of the CTL input section. A trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier, reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits and timer L as the PB-CTL signal.
Page 794 (1) CTL Detector If the CTL detector fails to detect a CTL pulse, it sets bit 1 of the CTL control register (CTCR) to high indicating that the pulse has not been detected. If a CTL pulse is detected after that, the bit is automatically cleared to 0. Duration used for determining detection or non-detection of the pulse depends on magnitude of phase shift of the last detected pulse from the reference phase (phase difference between REF30 and CTL signal).
Page 795 (2) PB-CTL Waveform Shaper in Slow Mode Operation If bit 0 in the CTL control register (CTCR) is set to slow mode, slow reset function is activated. In slow mode, if the falling edge is not detected within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset).
Page 796: Duty Discriminator
28.13.8 Duty Discriminator The duty discriminator circuit measures the period of the control signal recorded on the tape (PB-CTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag is set or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the duty cycle of the PB-CTL signal is equal to or above 44%, and is cleared to 0 when the duty cycle is below 43%.
Page 797 Input signal Short 1 pulse PB-CTL 25±0.5% Input signal Long 1 pulse PB-CTL 30±0.5% Input signal Short 0 pulse PB-CTL 57.5±0.5% Input signal Long 0 pulse PB-CTL 62.5±0.5% Input signal ASM Mark PB-CTL 67 to 70% Figure 28.55 PB-CTL Signal Duty Cycle Rev.
Page 798 Figure 28.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by counting with the 16-bit up/down counter, using a φs/4 clock for the up-count and a φs/5 clock for the down-count. An up-count is performed when the PB-CTL signal is high, and a down- count when low.
Page 799 (1) VISS (Index) Detect/Record Mode VISS detection is carried out by the VISS control circuit, which counts 1 pulses in the PB- CTL signal. If the pulse count detects any value set in the VISS interrupt setting bits (bits 5, 6 and 7 in the duty I/O register), an interrupt request is generated and the duty I/O flag is cleared to 0.
Page 800 (2) VASS Detect Mode VASS detection is carried out by the duty discriminator. Software can detect index sequences by reading the duty I/O flag at each CTL pulse. At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O flag, and simultaneously generates an interrupt request.
Page 801 (4) Detection of the Long/Short Pulse The Long/Short pulse is detected in PB mode by the L/S determination based on the comparison of the REC-CTL duty registers (RCDR2 to RCDR5) with the up/down counter and the results of the duty I/O flag. The results of the determination are stored in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting BTPR leftward at the same time.
Page 802: 28.13.9 Ctl Output Section
28.13.9 CTL Output Section An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the write control circuit onto the tape. The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and VASS sequences and ASM marks and the rewriting of VISS and VASS sequences.
Page 803 Internal bus RESET REF30X Clear RCDR1 RCDR2or4 RCDR3or5 UP/DOWN counter (12 bits) (12bit) (12bit) (12bit) Upper 12 bits Compare Compare Compare REC-CTL rise timing REC-CTL 1 pulse, REC-CTL 0 pulse fall ASM fall timing timing End of writing of one CTL pulse (except VISS) IRRCTL REF30X Counter...
Page 804 The 16-bit counter in the REC-CTL circuit continues counting on a clock derived by dividing the system clock φs (= f /2) by 4. The counter is cleared on the rise of REF30X in record mode, and on the rise of PB-CTL in rewrite mode. The REC-CTL match detection is carried out by comparing the counter value with each RCDR value.
Page 805: 28.13.10 Trapezoid Waveform Circuit
28.13.10 Trapezoid Waveform Circuit In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PB- CTL signal intact, but changes the duty cycle. In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5).
Page 806: 28.13.11 Note On Ctl Interrupt
28.13.11 Note on CTL Interrupt Following a reset, the CTL circuit is in the VASS detect (duty detect) mode. Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt request generated. If the interrupt request will be enabled, first clear the CTL interrupt request flag.
Page 807: Frequency Dividers
28.14 Frequency Dividers 28.14.1 Overview On-chip frequency dividers are provided for the pulse signal picked up from the control track during playback (PB-CTL signal), and the pulse signal received from the capstan motor (CFG signal). An on-chip noise canceller is provided for the drum motor pulse signal (DFG signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL signal, for use in capstan phase control during high-speed search, for example.
Page 808 • DVCTL control register (CTVC) Bit : — — — Initial value : — — — R/W : Note: * Initial value is uncertain. The DVCTL control register (CTVC) is a register consisting of the external input signal selection bit and the flags which show the CFG, HSW and CTL levels. Note: It has an undetermined value by a reset or stand-by.
Page 809 Bit 1: HSW Flag (HSW) Shows the level of the HSW signal selected by the VFF/NFF bit of the HSW mode register 2 (HSM2). Bit 1 Description HSW is at Low level (Initial value) HSW is at High level Bit 0: CTL Flag (CTL) Shows the CTL level.
Page 810 (3) Operation During playback, control pulses recorded on the tape are picked up by the control head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier, reshaped, then input to the CTL frequency divider as the PB-CTL signal. This circuit is employed when the control pulse (PB-CTL signal) is used for phase control of the capstan motor.
Page 811: 28.14.3 Cfg Frequency Divider
28.14.3 CFG Frequency Divider (1) Block Diagram Figure 28.65 shows a block diagram of the 7-bit CFG frequency divider and its mask timer. Internal bus · CDVC CDIVR(7bit) · CDVC · CDVC MCGin Edge Down counter (7 bits) select DVCFG Down counter (7 bits) DVCFG2 PB(ASM) REC...
Page 812 (2) Register Descriptions • Register configuration Table 28.23 shows the register configuration of the CFG frequency divider. Table 28.23 Register Configuration Name Abbrev. Size Initial Value Address DVCFG control register CDVC Byte H'60 F'FD09A CFG frequency division CDIVR1 Byte H'80 H'FD09B register 1 CFG frequency division...
Page 813 Bit 5: CFG Mask Status Bit (CMK) Indicates the status of the mask. It is initialized to 1 by a reset, stand-by or module stop. Bit 5 Description Indicates that the capstan mask timer has released masking Indicates that the capstan mask timer is currently masking (Initial value) Bit 4: CFG Mask Selection Bit (CMN) Selects the turning ON/OFF of the mask function.
Page 814 Bits 1 and 0: CFG Mask Timer Clock Selection Bits (CPS1, CPS0) Selects the clock source for the CFG mask timer. (φs = fosc/2) Bit 1 Bit 0 CPS1 CPS0 Description φs/1024 (Initial value) φs/512 φs/256 φs/128 Rev. 2.0, 11/00, page 787 of 1037...
Page 815 • CFG frequency division register 1 (CDIVR1) Bit : CDV16 CDV15 CDV14 CDV13 CDV12 CDV11 CDV10 — Initial value : — R/W : The CFG frequency division register 1 (CDIVR1) is an 8-bit write-only register to set the CFG division value (N-1 for N division). If a read is attempted, an undetermined value is read out.
Page 816 • DVCFG mask period register (CTMR) Bit : CPM5 CPM4 CPM3 CPM2 CPM1 CPM0 — — Initial value : — — R/W : The DVCFG mask period register (CTMR) is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. CTMR is a reload register for the mask timer (down counter).
Page 817 When the DVTRG bit in the CDVC register is set to 0, reloading is executed with the switchover timing from PB (ASM) mode to REC mode. To switch from REF30 to CREF, change the settings of bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR).
Page 818 • Mask timer The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock source. The mask timer is used for masking the DVCFG signal intended for controlling the capstan speeds. The capstan mask timer prevents edge detection to be carried out for an unnecessarily long duration by masking the edge detection for a certain period.
Page 819 Figures 28.68 and 28.69 show examples of CFG mask timer operations. CFG (racing) Edge detect Capstan motor Mask interval Mask interval mask timer DVCFG Cleared by writing 0 after reading 1 MCGin flag Figure 28.68 CFG Mask Timer Operation (When Capstan Motor is Racing) Edge detect Capstan motor Mask interval...
Page 820: 28.14.4 Dfg Noise Removal Circuit
28.14.4 DFG Noise Removal Circuit (1) Block Diagram Figure 28.70 shows the block diagram of the DFG noise removal circuit. Edge NCDFG detection Edge detection Delay circuit delay = 2 Figure 28.70 DFG Noise Removal Circuit (2) Register Descriptions • Register configuration Table 28.24 shows the register configuration of the DFG mask circuit.
Page 821 Bit 0: DFG Edge Selection Bit (DRF) Selects the edge of the NCDFG signal used in the drum speed error detector. Bit 0 Description Selects the rising edge of NCDFG signal (Initial value) Selects the falling edge of NCDFG signal (3) Description of Operation The DFG noise removal circuits generates a signal (NCDFG signal) with a delay circuit as a result of removing noise (signal fluctuation smaller than 2 φ) from the DFG signal.
Page 822: Sync Signal Detector
28.15 Sync Signal Detector 28.15.1 Overview This block performs detection of the horizontal sync signal (Hsync) and vertical sync signal (Vsync) from the composite sync signal (Csync), noise counting, and field detection. It detects the horizontal and vertical sync signals by setting threshold in the register and based on the servo clock (φs = fosc/2).
Page 823: Block Diagram
28.15.2 Block Diagram Figure 28.72 shows the block diagram of the sync signal detector. Figure 28.72 Block Diagram of the Sync Signal Detector Rev. 2.0, 11/00, page 796 of 1037...
Page 824: Pin Configuration
28.15.3 Pin Configuration Table 28.25 shows the pin configuration of the sync signal detector. Table 28.25 Pin Configuration Name Abbrev. Function Composite sync signal input pin Csync Input Composite sync signal input 28.15.4 Register Configuration Table 28.26 shows the register configuration of the sync signal detector. Table 28.26 Register Configuration Name Abbrev.
Page 825: Register Descriptions
28.15.5 Register Descriptions (1) Vertical Sync Signal Threshold Register (VTR) Bit : — — VTR5 VTR4 VTR3 VTR2 VTR1 VTR0 Initial value : R/ W : — — Sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal.
Page 826 (2) Horizontal Sync Signal Threshold Register (HTR) Bit : HTR3 HTR2 HTR1 HTR0 — — — — Initial value : R/W : — — — — Sets the threshold for the horizontal sync signal when the signal is detected from the composite sync signal.
Page 827 • Example The set values to detect the vertical and horizontal sync signals (SEPV and SEPH) from Csync are required to meet the following conditions. Assumed that the set values in the VTHR register were VVTH and HVTH, (VVTH-1) × 2/φs > Hpuls (HVTH-2) ×...
Page 828 (3) H Supplement Start Time Setting Register (HRTR) Bit : HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0 Initial value : R/W : Sets the timing to generate a supplementary pulse if a drop-out of a pulse of the horizontal sync signal occurred.
Page 829 (5) Noise Detection Window Setting Register (NWR) Bit : — — NWR5 NWR4 NWR3 NWR2 NWR1 NWR0 Initial value : R/W : — — NWR sets the period (window) when the drop-out of the pulse of the horizontal sync signal is detected and the noise is counted.
Page 830 (7) Sync Signal Control Register (SYNCR) Bit : — — — — NIS/VD NOIS SYCT Initial value : — — — — R/(W) * R/W : Note: * Only 0 can be written SYNCR controls the noise detection, field detection, polarity of the sync signal input, etc. SYNCR is an 8-bit register.
Page 831 Bit 1: Field Detection Flag (FLD) Indicates whether the field currently being scanned is even or odd. See figure 28.74. Bit 1 Description Odd field (Initial value) Even field Bit 0: Sync Signal Polarity Selection Bit (SYCT) Selects the polarity of the sync signal (Csync) to be input. Bit 0 SYCT Description...
Page 832 Composite sync signal (Csync) SEPV Noise detection window Field detection flag (FLD) Even field (a) Even field (EVEN) Composite sync signal (Csync) SEPV Noise detection window Field detection flag (FLD) Odd field (b) Odd field (ODD) Figure 28.74 Field Detection Rev.
Page 833: 28.15.6 Noise Detection
28.15.6 Noise Detection If drop-out of a pulse of the horizontal sync signal occurred, set a supplemented pulse at the timing set in HPWR and with the set pulse width. Set the noise detection window with HWR of about 1/4 of the horizontal sync signal, and the pulse with equal High and Low periods will be obtained.
Page 834 Drop-out of the horizontal Ignore signal during noise sync signal mask period. SEPH H counter H'00 H'E8 H reload counter Don't mask immediately Mask Mask Mask Mask after period period period period supplement Noise mask for H counter OSCH Mask Mask Mask Mask...
Page 835 (2) Operation to Detect Noise The noise detector considers an irregular pulse of the composite sync signal (Csync) and a chip of a pulse of the horizontal sync signal within a frame as noise. The noise counter takes counts of the irregular pulses during the High period of the noise detection window and the chips and drop-outs of the horizontal sync signal pulses during the Low period.
Page 836: 28.15.7 Sync Signal Detector Activation
28.15.7 Sync Signal Detector Activation The sync signal detector starts operation by release of reset, or by accepting input of a sync signal after its transition from power-down mode to active mode and release of module stop. The signal given to the detector is the polarity pulse assigned by the SYCT bit of the sync signal control register (SYNCR).
Page 837: Servo Interrupt
28.16 Servo Interrupt 28.16.1 Overview The interrupt exception processing of the servo module is started by one of ten factors, i.e. the drum speed error detector (×2), drum phase error detector, capstan speed error detector (×2), capstan phase error detector, HSW timing generator (×2), sync detector and CTL circuit. For these interrupt factors, see each of their circuit sections in this manual.
Page 838 Bit 7: Drum Phase Error Detection Interrupt Permission Bit (IEDRM3) Bit 7 IEDRM3 Description Prohibits the interrupt request through IRRDRM3 (Initial value) Permits the interrupt request through IRRDRM3 Bit 6: Drum Speed Error Detection (lock detection) Interrupt Permission Bit (IEDRM2) Bit 6 IEDRM2 Description...
Page 839 Bit 2: Capstan Speed Error Detection (OVF, latch) Interrupt Permission Bit (IECAP1) Bit 2 IECAP1 Description Prohibits the interrupt request through IRRCAP1 (Initial value) Permits the interrupt request through IRRCAP1 Bit 1: HSW Timing Generation (counter clear, capture) Interrupt Permission bit (IEHSW2) Bit 1 IEHSW2...
Page 840 (2) Servo Interrupt Permission Register 2 (SIENR2) Bit : — — — — — — IESNC IECTL Initial value : R/W : — — — — — — SIENR2 controls the permission and prohibition of the interrupt of the servo section. SIENR2 is an 8-bit readable/writable register.
Page 841 (3) Servo Interrupt Request Register 1 (SIRQR1) Bit : IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W : Note: * Only 0 can be written to clear the flag. SIRQR1 displays an occurrence of an interrupt request of the servo section.
Page 842 Bit 4: Capstan Phase Error Detector Interrupt Request Bit (IRRCAP3) Bit 4 IRRCAP3 Description No interrupt request from the capstan phase error detector (Initial value) Interrupt requested from the capstan phase error detector Bit 3: Capstan Speed Error Detector (lock detection) Interrupt Request Bit (IRRCAP2) Bit 3 IRRCAP2 Description...
Page 843 (4) Servo Interrupt Request Register 2 (SIRQR2) Bit : IRRSNC IRRCTL — — — — — — Initial value : R/(W) * R/(W) * — — — — — — R/W : Note: * Only 0 can be written to clear the flag. SIRQR2 displays an occurrence of an interrupt request of the servo section.
Page 844: Module Stop Control Reigster (Mstpcr)
28.17 Module Stop Control Reigster (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers, that perform module stop mode control.
Page 845 Rev. 2.0, 11/00, page 818 of 1037...
Page 846: Section 29 Electrical Characteristics
Section 29 Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 lists the absolute maximum ratings. Table 29.1 Absolute Maximum Ratings Item Symbol Value Unit −0.3 to +7.0 Power supply voltage −0.3 to Vcc+0.3 Input voltage (ports other than port 0) −0.3 to AVcc+0.3 Input voltage (port 0) −0.3 to +7.0...
Page 847: Electrical Characteristics Of Hd64F2194
29.2 Electrical Characteristics of HD64F2194 29.2.1 DC Characteristics of HD64F2194 Table 29.2 DC Characteristics of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Item Symbol Applicable Pins Test Conditions Min...
Page 848 Values Test Item Symbol Applicable Pins Conditions Unit Notes  Input low Vcc=2.7 to 5.5V –0.3 0.1 Vcc voltage ,& −0.3  , FWE, 0.2 Vcc ,54 ,54 −0.3  Vcc=2.7 to 5.5V 0.1 Vcc −0.3  SCK1, SCK2, SI1, SI2, 0.2 Vcc &6 , FTIA, FTIB, FTIC,...
Page 849 Values Item Symbol Applicable Pins Test Conditions Min Unit Notes   Output SO1, SO2, SCK1, =1.6mA SCK2, PWM1, PWM2,   =0.4mA voltage PWM3, PWM4, Vcc=2.7 to 5.5V PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37,...
Page 850 Values Test Item Symbol Applicable Pins Conditions Unit Notes −Ip  µA Pull-up P10 to P17, Vcc=5.0V, Note 1 P20 to P27, Vin=0V current P30 to P37,   Input All input pins except fin=1 MHz, capaci- power supply, P13, P23, Vin=0V, tance P24 and analog system...
Page 851 Values Test Item Symbol Applicable Pins Conditions Unit Notes  µA Vcc=2.7V, Watch Note 2 WATCH With 32kHz mode crystal current oscillator dissipa-   µA Vcc=5.0V, Reference tion With 32kHz value crystal Note 2 oscillator   µA X1=Vcc, Standby Note 2 STBY...
Page 852 Table 29.4 Bus Drive Characteristics of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Applicable pin: SCL, SDA Values Test Item Symbol Applicable Pins Conditions Unit Notes −...
Page 853: Allowable Output Currents Of Hd64F2194, Hd64F2194C
29.2.2 Allowable Output Currents of HD64F2194, HD64F2194C The specifications for the digital pins are shown below. Table 29.5 Allowable Output Currents (Conditions: Vcc = 2.7 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C) Item Symbol Value Unit Notes Allowable input current (to chip)
Page 854: Ac Characteristics Of Hd64F2194, Hd64F2194C
29.2.3 AC Characteristics of HD64F2194, HD64F2194C Table 29.6 AC Characteristics of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Item Symbol Pins Test Conditions Min Unit...
Page 855 Values Applicable Item Symbol Pins Test Conditions Min Unit Figure   pin low level Vcc=2.7V to Figure width 5.5V 29.4 ,54 ,54   Input pin high level Vcc=2.7V to Figure ,& width 5.5V 29.5 subcyc $'75* TMBI, FTIA, FTIB, FTIC, FTID, TRIG ,54...
Page 856 4.0V OSC1 (Internal) DEXT Note: * The t includes the RES pin Low level width 20 t DEXT Figure 29.3 External Clock Stabilization Delay Timing Figure 29.4 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG Figure 29.5 Input Timing Rev.
Page 857: Serial Interface Timing Of Hd64F2194, Hd64F2194C
29.2.4 Serial Interface Timing of HD64F2194, HD64F2194C Table 29.7 Serial Interface Timing of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Item Symbol Pins...
Page 858 SCKW scyc or V SCK1 or V SCKr SCKf Figure 29.6 SCK1 Clock Timing SCK1, SCK2 SO1, SI1, Figure 29.7 SCI I/O Timing/Clock Synchronization Mode SCK2 Figure 29.8 SCI2 Chip Select Timing Rev. 2.0, 11/00, page 831 of 1037...
Page 859 2.4k LSI output pin 30pF Timing reference level : 2.0V : 0.8V Figure 29.9 Output Load Conditions Rev. 2.0, 11/00, page 832 of 1037...
Page 860 Table 29.8 I C Bus Interface Timing of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test Item Symbol Conditions Unit Figure ...
Page 861 SCLH STOS STAH STAS Sr * SCLL SDAS SDAH Note: * S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 29.10 I C Bus Interface I/O Timing Rev. 2.0, 11/00, page 834 of 1037...
Page 862: A/D Converter Characteristics Of Hd64F2194, Hd64F2194C
29.2.5 A/D Converter Characteristics of HD64F2194, HD64F2194C Table 29.9 A/D Converter Characteristics of HD64F2194, HD64F2194C (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable Item Symbol Pins...
Page 863: Servo Section Electrical Characteristics Of Hd64F2194, Hd64F2194C
29.2.6 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C Table 29.10 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Reference Values Applicable Item Symbol...
Page 864 Reference Values Applicable Item Symbol Pins Test Conditions Unit Note   CFG pin bias voltage   CFG input level AC coupling, C=1µF Typ, f=1kHz   CFG input kΩ impedance Rise threshold level   CFG input V+THCF 2.25 threshold voltage ...
Page 865 Table 29.11 Servo Section Electrical Characteristics of HD64F2194, HD64F2194C (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Values Applicable Item Symbol Pins Test Conditions Unit Note  Digital input high COMP, Vcc+ voltage...
Page 866: Flash Memory Characteristics
29.2.7 FLASH Memory Characteristics Table 29.12 shows the flash memory characteristics. Table 29.12 Flash Memory Characteristics (Preliminary) Conditions: Vcc = 5.0 V ± 10%, AVcc = 5.0 V ± 10%, Vss = AVss = 0 V, Ta = 0 to +75°C (operating temperature range at programming/erasing) Test Item...
Page 867: Usage Note
3. Time to erase 1 block (total time of setting E-bit of the flash memory control register. Erasing verify time is not included). (max.)) = Wait time after P-bit setting (z) × Maximum 4. Maximum programming time (t No. of programming (N) 5.
Page 868: Electrical Characteristics Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3 Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A 29.3.1 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.13 DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Item...
Page 869 Values Item Symbol Applicable Pins Test Conditions Min Unit Notes −0.3  Input low Vcc=2.5 to 5.5V 0.1 Vcc voltage ,& ,54 −0.3  0.2 Vcc ,54 −0.3  Vcc=2.5 to 5.5V 0.1 Vcc −0.3  SCK1, SCK2, SI1, SI2, 0.2 Vcc &6 , FTIA, FTIB, FTIC,...
Page 870 Values Item Symbol Applicable Pins Test Conditions Min Unit Notes   Output SO1, SO2, SCK1, =1.6mA SCK2, PWM1, PWM2,   =0.4mA voltage PWM3, PWM4, Vcc=2.5 to 5.5V PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37,...
Page 871 Values Test Item Symbol Applicable Pins Conditions Unit Notes −Ip  µA Pull-up P10 to P17, Vcc=5.0V, Note 1 P20 to P27, Vin=0V current P30 to P37   Input All input pins except fin=1 MHz, capacity power supply, P23, P24 Vin=0V, and analog system pins Ta=25°C...
Page 872 Values Test Item Symbol Applicable Pins Conditions Unit Notes  µA Vcc=2.5V, Watch Note 2 WATCH With 32kHz mode crystal current oscillator dissipa-   µA Vcc=5.0V, Reference tion With 32kHz value crystal Note 2 oscillator   µA X1=Vcc, Standby Note 2 STBY...
Page 873 Table 29.15 Bus Drive Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Applicable pin: SCL, SDA Values Test Item Symbol...
Page 874: Allowable Output Currents Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A The specifications for the digital pins are shown below. Table 29.16 Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = 2.5 to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C) Item Symbol Value...
Page 875: Ac Characteristics Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.17 AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 876 Values Applicable Item Symbol Pins Test Conditions Min Unit Figure   Subclock input rise Vcc=2.5 to 5.5V Figure EXCLr time 29.12   Subclock input fall Vcc=2.5 to 5.5V EXCLf time   pin low level Vcc=2.5V to Figure width 5.5V 29.14...
Page 877 subcyc EXCLH EXCLL EXCLr EXCLf Figure 29.12 Subclock Input Timing 4.0V OSC1 (Internal) DEXT Note: * The t includes the RES pin Low level width 20 t DEXT Figure 29.13 External Clock Stabilization Delay Timing Rev. 2.0, 11/00, page 850 of 1037...
Page 878 Figure 29.14 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG Figure 29.15 Input Timing Rev. 2.0, 11/00, page 851 of 1037...
Page 879: Serial Interface Timing Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.18 Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 880 SCKW scyc or V SCK1 or V SCKr SCKf Figure 29.16 SCK1 Clock Timing SCK1, SCK2 SO1, SI1, Figure 29.17 SCI I/O Timing/Clock Synchronization Mode SCK2 Figure 29.18 SCI2 Chip Select Timing Rev. 2.0, 11/00, page 853 of 1037...
Page 881 2.4k LSI output pin 30 pF Timing reference level : 2.0 V : 0.8 V Figure 29.19 Output Load Conditions Rev. 2.0, 11/00, page 854 of 1037...
Page 882 Table 29.19 I C Bus Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Test Item Symbol...
Page 883 SCLH STOS STAH STAS Sr * SCLL SDAS SDAH Note: * S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions Figure 29.20 I C Bus Interface I/O Timing Rev. 2.0, 11/00, page 856 of 1037...
Page 884: A/D Converter Characteristics Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.20 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless otherwise specified.) Values Applicable...
Page 885: Servo Section Electrical Characteristics Of Hd6432194, Hd6432193, Hd6432192, Hd6432191, Hd6432194C, Hd6432194B, And Hd6432194A
29.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A Table 29.21 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Reference Values Applicable Item...
Page 886 Reference Values Applicable Item Symbol Pins Test Conditions Unit Note   CTL reference CTLREF output voltage   CFG pin bias voltage   CFG input level AC coupling, C=1µF Typ, f=1kHz   CFG input kΩ impedance Rise threshold level  ...
Page 887 Table 29.22 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.) Values Applicable Item Symbol Pins Test Conditions Unit Note ...
Page 888: Appendix A Instruction Set
Appendix A Instruction Set Instructions [Operation Notation] General register (destination) General register (source) General register General register (32-bit register) Multiplication-Addition register (32-bit register) (EAd) Destination operand (EAs) Source operand Extend register Condition code register N (negative flag) in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter...
Page 889 Notes: 1. General register is 8-bit (R0H to R7H, R0L to R7L), 16-bit (R0 to R7) or 32-bit (ER0 to ER7). 2. MAC register cannot be used in this LSI. [Condition Code Notation] Symbol Description Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Always set to 1...
Page 890 Table A.1 List of Instruction Set (1) Data Transfer Instruction Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic Size States * H N Z V C Advanced Mode MOV.B #xx:8,Rd #xx:8 Rd8 — — — MOV.B Rs,Rd Rs8 Rd8 —...
Page 891 (2) Arithmetic Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States * Mnemonic Size H N Z V C Advanced Mode — ADD.B #xx:8,Rd Rd8+#xx:8 Rd8 — ADD.B Rs,Rd Rd8+Rs8 Rd8 — ADD.W #xx:16,Rd Rd16+#xx:16 Rd16 ADD.W Rs,Rd —...
Page 892 (3) Logic Operations Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States * Mnemonic Size H N Z V C Advanced Mode AND.B #xx:8,Rd Rd8 #xx:8 Rd8 — — — AND.B Rs,Rd Rd8 Rs8 Rd8 —...
Page 893 (4) Shift Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States * Mnemonic Size H N Z V C Advanced Mode — — SHAL SHAL.B Rd SHAL.B #2,Rd — — SHAL.W Rd — — — —...
Page 894 (5) Bit Manipulation Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States * Mnemonic Size H N Z V C Advanced Mode BSET BSET #xx:3,Rd — — — — — — (#xx:3 of Rd8) 1 BSET #xx:3,@ERd —...
Page 895 Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code States * Mnemonic Size H N Z V C Advanced Mode — — — — — BIAND BIAND #xx:3,Rd C [~(#xx:3 of Rd8)] C — — — — —...
Page 896 (6) Branch Instructions Addressing Mode and Instruction Length (Bytes) No of Operation Execution Operation Code States * Mnemonic Size Branch H N Z V C Advanced Mode Condition — — — — — — — BRA d:8(BT d:8) if condition is true then Always —...
Page 897 (7) System Control Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Code Operation States * Mnemonic Size H N Z V C Advanced Mode — — — — — TRAPA TRAPA #xx:2 — PC @-SP,CCR @-SP, 8 [9] EXR @-SP,<Vector>...
Page 898 (8) Block Transfer Instructions Addressing Mode and Instruction Length (Bytes) No of Condition Execution Operation Code Mnemonic States * Size H N Z V C Advanced Mode — — — — — — EEPMOV EEPMOV.B — if R4L 0 4+2n * Repeat @ER5 @ER6 ER5+1 ER5 ER6+1 ER6...
Page 899: Instruction Codes
Instruction Codes Rev. 2.0, 11/00, page 872 of 1037...
Page 900 Rev. 2.0, 11/00, page 873 of 1037...
Page 901 Rev. 2.0, 11/00, page 874 of 1037...
Page 902 Rev. 2.0, 11/00, page 875 of 1037...
Page 903 Rev. 2.0, 11/00, page 876 of 1037...
Page 904 Rev. 2.0, 11/00, page 877 of 1037...
Page 905 Rev. 2.0, 11/00, page 878 of 1037...
Page 906 Rev. 2.0, 11/00, page 879 of 1037...
Page 907 Rev. 2.0, 11/00, page 880 of 1037...
Page 908 [Legend] IMM: Immediate data (2, 3, 8, 16, 32 bits) abs: Absolute address (8, 16, 24, 32 bits) disp: Displacement (8, 16, 32 bits) rs, rd, rn: Register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and rn correspond to the operand type Rs, Rd, and Rn respectively.) ers, erd, ern, erm: Register fields (address register or 32-bit register is selected in 3 bits.
Page 909: Operation Code Map
Operation Code Map Table A.3 shows an operation code map. Rev. 2.0, 11/00, page 882 of 1037...
Page 910 Rev. 2.0, 11/00, page 883 of 1037...
Page 911 Rev. 2.0, 11/00, page 884 of 1037...
Page 912 Rev. 2.0, 11/00, page 885 of 1037...
Page 913: Number Of Execution States
Number of Execution States This section explains execution state and how to calculate the number of execution states for each instruction of the H8S/2194 CPU. Table A.5 indicates number of cycles of instruction fetch and data read/write during instruction execution, and table A.4 indicates number of states required for each instruction size. The number of execution states can be obtained from the equation below.
Page 914 Table A.4 Number of States Required for Each Execution Status (Cycle) Target of Access On-Chip Supporting Module Execution Status (Cycle) On-Chip Memory 8-bit bus 16-bit bus Instruction fetch S — — Branch address read S Stack operation S Byte data access S Word data access S Internal operation S Rev.
Page 915 Table A.5 Instruction Execution Status (No. of Cycles) Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs, Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd...
Page 916 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd...
Page 917 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8...
Page 918 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2 ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B 2n+2 EEPMOV.W 2n+2 EXTS EXTS.W Rd EXTS.L ERd EXTU...
Page 919 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16...
Page 920 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn...
Page 921 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd...
Page 922 Branch Instruction Address Stack Byte Data Word Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1.
Page 923: Bus Status During Instruction Execution
Bus Status During Instruction Execution Table A.6 indicates execution status of each instruction available in this LSI. For the number of states required for each execution status, see table A.4, Number of States Required for Each Execution Status (Cycle). [How to see the table] Order of execution Instruction Internal operation...
Page 924 Table A.6 Instruction Execution Status Instruction ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd...
Page 925 Instruction BLT d:16 R:W 2nd Internal R:W EA operation 1 state BGT d:16 R:W 2nd Internal R:W EA operation 1 state BLE d:16 R:W 2nd Internal R:W EA operation 1 state BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8...
Page 926 Instruction BNOT Rn @aa:16 R:W 2nd R:W 3rd R:B:W EA R:W:M NEXT W:B EA BNOT Rn @aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BOR #xx:3,Rd R:W NEXT BOR #xx:3,ERd R:W 2nd R:B EA R:W:M NEXT BOR #xx:3,@aa:8 R:W 2nd R:B EA...
Page 927 Instruction DEC.W #1/2,Rd R:W NEXT DEC.W #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation 19 state DIVXU.B Rs,Rd R:W NEXT Internal operation 11 state DIVXU.W Rs,ERd R:W NEXT Internal operation 19 state R:B EAs * R:B EAd *...
Page 928 Instruction MOV.B #xx:8,Rd R:W NEXT MOV.B Rs,Rd R:W NEXT MOV.B @ERs,Rd R:W NEXT R:B EA MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA MOV.B @ERs+,Rd R:W NEXT Internal R:B EA operation 1 state...
Page 929 Instruction MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2 MOVFPE @aa:16,Rd Cannot be used in this LSI. MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state MULXS.W Rs,Rd...
Page 930 Instruction ROTXR.L ERd R:W NEXT ROTXR.L #2.ERd R:W NEXT R:W NEXT R:W stack(H) R:W stack(L) Internal stack(EXR) operation 1 state R:W NEXT R:W:M R:W stack(L) Internal stack(H) operation 1 state SHAL.B Rd R:W NEXT SHAL B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.W #2,Rd R:W NEXT...
Page 931 Instruction STMAC MACH,ERd Cannot be used in this LSI. STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3nd R:W NEXT SUB.L ERs,ERd R:W NEXT SUB #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd...
Page 932: Change Of Condition Codes
Change of Condition Codes This section explains change of condition codes after instruction execution of the CPU. Legend of the following tables is as follows. m = 31: Longword size m = 15: Word size m = 7: Byte size Bit i of source operand Bit i of destination operand Bit i of result...
Page 933 Table A.7 Change of Condition Code Instruc- tion Definition H=Sm-4⋅Dm-4+Dm-4⋅ +Sm-4⋅ 5P 5P N=Rm ⋅ ⋅ ⋅ RRRRRR 5P ⋅ ⋅Rm V=Sm⋅Dm⋅ C=Sm⋅Dm+Dm⋅ +Sm⋅ − − − − − ADDS ADDX H=Sm-4⋅Dm-4+Dm-4⋅ +Sm-4⋅ 5P 5P N=Rm ⋅ ⋅ Z=Z'⋅ RRRRRR ⋅...
Page 934 Instruc- tion Definition ⋅Rm-4+Sm-4⋅Rm-4 H=Sm-4⋅ 'P 'P N=Rm ⋅ ⋅ ⋅ RRRRRR 5P ⋅Dm⋅ ⋅Rm +Sm⋅ ⋅Rm+Sm⋅Rm C=Sm⋅ N=Rm ⋅ ⋅ ⋅ RRRRRR 5P C: Decimal addition carry N=Rm ⋅ ⋅ ⋅ RRRRRR 5P C: Decimal subtraction borrow − − N=Rm ⋅...
Page 935 Instruc- tion Definition MOVFPE Cannot be used in this LSI. MOVTPE − − − MULXS N=R2m ⋅ ⋅ ⋅ RRRRRR 5P − − − − − MULXU H=Dm-4+Rm-4 N=Rm ⋅ ⋅ ⋅ RRRRRR 5P V=Dm⋅Rm C=Dm+Rm − − − − −...
Page 936 Instruc- tion Definition − SHAL N=Rm ⋅ ⋅ ⋅ RRRRRR 5P ⋅ V=Dm⋅Dm-1+ (In case of 1 bit) 'P ⋅ ⋅ V=Dm⋅Dm-1⋅Dm-2⋅ 'P 'P (In case of 2bits) C=Dm , C=Dm-1 (In case of 1 bit) (In case of 2 bits) −...
Page 937: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Register Module Address * Name Access Width Name H'D000 DGKp DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8 Drum digital filter H'D001 DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0 H'D002 DGKs DGKs15 DGKs14 DGKs13 DGKs12 DGKs11...
Page 938 Register Module Address * Name Access Width Name H'D030 DFPR DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8 Drum error detector H'D031 DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0 H'D032 DFER DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8 H'D033 DFER7 DFER6...
Page 939 Register Module Address * Name Access Width Name − − − − H'D070 XR11 XR10 X-value, TRK-value H'D071 − − − − H'D072 TRDR TRD11 TRD10 TRD9 TRD8 H'D073 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 − H'D074 XTCR CAPRF TRK/ EXC/REF...
Page 940 Register Module Address * Name Access Width Name − − H'D0B0 VTR5 VTR4 VTR3 VTR2 VTR1 VTR0 Sync detector − − − − H'D0B1 HTR3 HTR2 HTR1 HTR0 H'D0B2 HRTR HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0 − − −...
Page 941 Register Module Address * Name Access Width Name H'D100 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Timer X1 * OCRA and H'D101 TCSRX ICFA ICFB ICFC ICFD OCFA OCFB CCLRA OCRB addresses H'D102 FRCH 8/16 FRCH7 FRCH6 FRCH5 FRCH4 FRCH3 FRCH2...
Page 942 Register Module Address * Name Access Width Name H'D130 ADRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2       H'D131 ADRL ADR1 ADR0 H'D132 AHRH AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2   ...
Page 943 Register Module Address * Name Access Width Name H'FFD0 PMR3 PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Port mode register H'FFD1 PCR1 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Port control register H'FFD2 PCR2 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21...
Page 944: Function List
Function List H'D000: Gain Constant DGKp: Drum Digital Filter H'D001: Gain Constant DGKp: Drum Digital Filter H'D002: Gain Constant DGKs: Drum Digital Filter H'D003: Gain Constant DGKs: Drum Digital Filter Bit : Initial value : R/W : H'D004: Coefficient DAp: Drum Digital Filter H'D005: Coefficient DAp: Drum Digital Filter H'D006: Coefficient...
Page 945 H'D00C: Offset DOfp: Drum Digital Filter H'D00D: Offset DOfp: Drum Digital Filter H'D00E: Offset DOfs: Drum Digital Filter H'D00F: Offset DOfs: Drum Digital Filter Bit : Initial value : R/W : H'D010: Gain Constant CGKp: Capstan Digital Filter H'D011: Gain Constant CGKp: Capstan Digital Filter H'D012: Gain Constant CGKs: Capstan Digital Filter...
Page 946 H'D014: Coefficient CAp: Capstan Digital Filter H'D015: Coefficient CAp: Capstan Digital Filter H'D016: Coefficient CBp: Capstan Digital Filter H'D017: Coefficient CBp: Capstan Digital Filter H'D018: Coefficient CAs: Capstan Digital Filter H'D019: Coefficient CAs: Capstan Digital Filter H'D01A: Coefficient CBs: Capstan Digital Filter H'D01B: Coefficient CBs: Capstan Digital Filter Bit : Initial value :...
Page 947 H'D020: Delay Initialization Register DZs: Digital filter H'D021: Delay Initialization Register DZs: Digital filter H'D022: Delay Initialization Register DZp: Digital filter H'D023: Delay Initialization Register DZp: Digital filter H'D024: Delay Initialization Register CZs: Digital filter H'D025: Delay Initialization Register CZs: Digital filter H'D026: Delay Initialization Register CZp: Digital filter H'D027: Delay Initialization Register CZp: Digital filter Bit :...
Page 948 H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter Bit : DROV DPHA DZPON DZSON DSG2 DSG1 DSG0 Initial value : R/(W) * R/(W) R/W : Drum system gain control bit DSG2 DSG1 DSG0 Description x 16 (x 32) * (x 64) * Invalid (do not set) Note: * Optional...
Page 949 H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter Bit : CROV CPHA CZPON CZSON CSG2 CSG1 CSG0 Initial value : R/(W) * R/(W) R/W : Capstan system gain control bit CSG2 CSG1 CSG0 Description x 16 (x 32) * (x 64) * Invalid (do not set) Capstan speed system Z...
Page 950 H'D02A: Digital Filter Control Register DFUCR: Digital Filter Bit : PTON CP/DP CFEPS DFEPS CFESS DFESS Initial value : R/W : Drum speed system error data transfer bit 0 Transfer data by NCDFG signal latch. 1 Transfer data at the time of error data write.
Page 951 H'D034: DFG Lock Upper Data Register DFRUDR: Drum Error Detector H'D035: DFG Lock Upper Data Register DFRUDR: Drum Error Detector Bit : Initial value : R/W : H'D036: DFG Lock Lower Data Register DFRLDR: Drum Error Detector H'D037: DFG Lock Lower Data Register DFRLDR: Drum Error Detector Bit : Initial value : R/W :...
Page 952 H'D038: Drum Speed Error Detection Control Register DFVCR: Drum Error Detector Bit : DFCS1 DFCS0 DFOVF DFRFON DF-R/UNR DPCNT DFRCS1 DFRCS0 Initial value : R/(W) (R)/W (R)/W R/W : Drum lock counter setting bit DFRCS1 DFRCS0 Description Underflow by 1 lock detection Underflow by 2 lock detections Underflow by 3 lock detections Underflow by 4 lock detections...
Page 953 H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Error Detector Bit : — — — DPCS1 DPCS0 DPOVF HSWES Initial value : R/(W) * — — — R/W : Edge select bit Latch at rising edge Latch at falling edge Error data latch signal select bit HSW (VideoFF) signal NHSW (NarrowFF) signal...
Page 954 H'D03D: Drum Phase Error Data Register 1 DPER1: Drum Error Detector Bit : — — — — Initial value : R * /W R * /W R * /W R * /W — — — — R/W : H'D03E: Drum Phase Error Data Register 2 DPER2: Drum Error Detector Bit : Initial value : R * /W...
Page 955 H'D058: Capstan Speed Error Detection Control Register CFVCR: Capstan Error Detector Bit : CFCS1 CFCS0 CFOVF CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0 Initial value : R/(W) (R)/W (R)/W R/W : Capstan lock counter setting bit CFRCS1 CFRCS0 Description Underflow by 1 lock detection Underflow by 2 lock detections Underflow by 3 lock detections Underflow by 4 lock detections...
Page 956 H'D059: Capstan Phase Error Detection Control Register CPGCR: Capstan Error Detector Bit : — — — CPCS1 CPCS0 CPOVF CR/RF SELCFG2 Initial value : R/(W) * — — — R/W : Preset, latch signal select bit Preset by CAPREF30 signal and latch by DVCTL signal Preset by REF30P signal and latch by DVCFG2 signal Preset signal select bit Preset by REF30P signal...
Page 957 H'D05D: Capstan Phase Error Data Register 1 CPER1: Capstan Error Detector Bit : — — — — Initial value : R * /W R * /W R * /W R * /W — — — — R/W : Note: * Note that only detected error data can be read. H'D05E: Capstan Phase Error Data Register 2 CPER2: Capstan Error Detector Bit : Initial value :...
Page 958 H'D060: HSW Mode Register 1 HSM1: HSW Timing Generator Bit : EMPB EMPA OVWB OVWA CLRB CLRA Initial value : R/(W) * R/(W) * R/W : FIFO1 pointer clear Normal operation Clear FIFO1 pointer FIFO2 pointer clear Normal operation Clear FIFO2 pointer FIFO1 overwrite flag Normal operation Data is written to FIFO1 while it is full.
Page 959 H'D061: HSW Mode Register 2 HSM2: HSW Timing Generator Bit : FGR20FF ISEL1 SOFG VFF/NFF Initial value : R/W : VideoFF/NarrowFF output switchover bit VideoFF output NarrowFF output Output FIFO group flag Outputting pattern by FIFO1 Outputting pattern by FIFO2 FIFO output group select bit 20-level output by FIFO1 and FIFO2 10-level output by FIFO1 only...
Page 960 H'D062: HSW Loop Stage Setting Register HSLP: HSW Timing Generator Bit : LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0 Initial value : R/W : FIFO1 stage setting bit HSM2 HSLP Description Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 LOA3 LOA2...
Page 961 H'D064: FIFO Output Pattern Register 1 FPDRA: HSW Timing Generator Bit : — ADTRGA STRIGA NarrowFFA VFFA AFFA VpulseA MlevelA Initial value : R/W : — Bit : PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0 Initial value : R/W : H'D066: FIFO Timing Pattern Register 1 FTPRA: HSW Timing Generator Bit : FTPRA15 FTPRA14...
Page 962 H'D06A: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator Bit : FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0 Initial value : R/W : Note: * Undetermined H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Generator Bit : ISEL2 CCLR...
Page 963 H'D06E: Special Effect Playback Control Register CHCR: 4-head Special Effect Playback Circuit Bit : HSWPOL SIG3 SIG2 SIG1 SIG0 Initial value : R/W : Signal control bits SIG3 SIG2 SIG1 SIG0 Output pin C.Rotary H.Amp SW HSW EX-OR COMP COMP HSW EX-NOR COMP COMP HSW EX-OR RTP0...
Page 964 H'D06F: Additional V Control Register ADDVR: Additional V Signal Generator Bit : — — — HMSK VPON Initial value : R/W : — — — Additional V output control bits VPON Description Low level Negative polarity (Figure 28.46) Positive polarity (Figure 28.45) Immediate level (high-impedance when HiZ bit = 1) High level...
Page 965 H'D074: X-Value/TRK-Value Control Register XTCR: X-Value, TRK-Value Adjustment Circuit Bit : — CAPRF AT/MU TRK/X EXC/REF DVREF1 DVREF0 Initial value : — R/W : REF30P frequency division rate select bit DVREF1 DVREF0 Description 1-division 2-division 3-division 4-division Clock source select bit 0 φs 1 φs/2 Reference signal select bit...
Page 966 H'D07A: Drum 12-Bit PWM Control Registor DPWCR: Drum 12-Bit PWM Bit : DPOL DHiZ DH/L DSF/DF DCK2 DCK1 DCK0 Initial value : R/W : Carrier frequency select bits Carrier frequency select bits φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 φ/128 (Do not set) Output data select bit Modulate error data from digital filter circuit Modulate data written in data register...
Page 967 H'D07C: Capstan 12-Bit PWM Data Register CPWDR: Capstan 12-Bit PWM Bit : — — — — CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Initial value : — — — — R/W : H'D080: CTL Control Register CTCR: CTL Circuit Bit : NT/PL FSLC...
Page 968 H'D081: CTL Mode Register CTLM: CTL Circuit Bit : REC/PB FW/RV Initial value : R/W : CTL mode select bits Direction bit 0 FORWARD 1 REVERSE Record/playback mode bits REC/PB Description Playback mode (PLAYBACK) Record mode (RECORD) Assemble mode Invalid (do not set) H'D082: REC-CTL Duty Data Register 1 RCDR1: CTL Circuit Bit : —...
Page 969 H'D088: REC-CTL Duty Data Register 4 RCDR4: CTL Circuit Bit : — — — — CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 Initial value : — — — — R/W : H'D08A: REC-CTL Duty Data Register 5 RCDR5: CTL Circuit Bit : —...
Page 970 H'D08D: Bit Pattern Register BTPR: CTL Circuit Bit : LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0 Initial value : R * /W R * /W R * /W R * /W R * /W R * /W R * /W R * /W R/W : Note: * Writes are disabled during bit pattern detection.
Page 971 H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator Bit : OD/EV Initial value : R/W : VideoFF edge select bit 0 Set at VideoFF signal rising 1 Set at VideoFF signal falling VideoFF counter set 0 VideoFF signal turns counter set OFF 1 VideoFF signal turns counter set OFF ODD/EVEN edge switchoverselect bit 0 Generated at field signal rising (EVEN)
Page 972 H'D098: DVCTL Control Register CTVC: Frequency Divider Bit : — — — Initial value : — — — R/W : CTL flag 0 REC or PB-CTL level is low 1 REC or PB-CTL level is high HSW flag 0 HSW level is low 1 HSW level is high CFG flag 0 CFG level is low...
Page 973 H'D09A: DVCFG Control Register CDVC: Frequency Divider Bit : MCGin — DVTRG CPS1 CPS0 Initial value : R/W * — R/W : CFG mask timer clock select bit CPS1 CPS0 Description φs/1024 φs/512 φs/256 φs/128 CFG frequency division edge select bit 0 Execute frequency division operation at CFG rising edge 1 Execute frequency division operation at CFG rising and falling edges...
Page 974 H'D09D: DVCFG Mask Interval Register CTMR: Frequency Divider Bit : — — CPM5 CPM4 CPM3 CPM2 CPM1 CPM0 Initial value : — — R/W : H'D09E: FG Control Register FGCR: Frequency Divider Bit : — — — — — — —...
Page 975 H'D0A1: Servo Control Register SPCR: Servo Port Bit : — — — SPCR4 SPCR3 SPCR2 SPCR1 SPCR0 Initial value : — — — R/W : SPCRn Description PSn pin functions as input pin PSn pin functions as output pin H'D0A2: Servo Data Register SPDR: Servo Port Controller Bit : —...
Page 976 H'D0A4: CTL Gain Control Register CTLGR: Servo Port Bit : — — CTLE/A CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0 Initial value : — — R/W : CTL amp gain setting bit CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL outpu gain 34.0 dB 36.5 dB 39.0 dB 41.5 dB 44.0 dB...
Page 977 H'D0B1: Horizontal Sync Signal Threshold Value Register HTR: Sync Detector (Servo) Bit : — — — — HTR3 HTR2 HTR1 HTR0 Initial value : — — — — R/W : H'D0B2: H Pulse Adjustment Start Time Setting Register HRTR: Sync Detector (Servo) Bit : HRTR7 HRTR6...
Page 978 H'D0B6: Sync Signal Control Register SYNCR: Sync Detector (Servo) Bit : — — — — NIS/VD NOIS SYCT Initial value : R/(W) * — — — — R/W : Sync signal polarity select bit SYCT Description Polarity Positive Negative Field detection flag 0 Odd field 1 Even field Noise detection flag...
Page 979 H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt Bit : IEDRM3 IEDRM2 IEDRM1 IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1 Initial value : R/W : HSW timing generator (OVW, match, STRIG) interrupt enable bit 0 Interrupt request is disabled by IRRHSW1 1 Interrupt request is enabled by IRRHSW1 HSW timing generation (counter clear, capture) interrupt enable bit...
Page 980 H'D0B9: Servo Interrupt Enable Register 2 SIENR2: Servo Interrupt Bit : — — — — — — IESNC IECTL Initial value : — — — — — — R/W : CTL interrupt enable bit 0 Interrupt request is disabled by IRRCTL 1 Interrupt request is enabled by IRRCTL Vertical sync signal interrupt enable bit...
Page 981 H'D0BA: Servo Interrupt Request Register 1 SIRQR1: Servo Interrupt Bit : IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W : HSW timing generator (OVW, match, STRIG) interrupt request bit 0 HSW timing generator (OVM, match, STRIG)
Page 982 H'D0BB: Servo Interrupt Request Register 2 SIRQR2: Servo Interrupt Bit : — — — — — — IRRSNC IRRCTL Initial value : R/(W) * R/(W) * — — — — — — R/W : CTL interrupt request bit 0 CTL interrupt request is not generated 1 CTL interrupt request is generated...
Page 983 H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2 Bit : — TEIE ABTIE GAP1 GAP0 CKS2 CKS1 CKS0 Initial value : — R/W : Transfer clock select bits CKS2 CKS1 CKS0 SCK2 pin Clock source Prescaler frequency Transfer clock frequency division rate φ...
Page 984 H'D0E3: Serial Control Status Register 2 SCSR2: 32-Byte Buffer SCI2 Bit : — — ORER Initial value : R/(W) * R/(W) * R/(W) * R/(W) * — — R/W : Start flag 0 Read: Transfer stops Write: Transfer aborted and SCI2 initialized 1 Read: Transfer in progress, or CS input standby...
Page 985 H'D100: Timer Interrupt Enable Register ITER: Timer X1 Bit : ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Initial value : R/W : Input capture input select A bit FTIA pin input is selected for input capture A input HSW is selected for input capture A input Output compare interrupt enable bit OCFC interrupt request...
Page 986 H'D101: Timer Control/Status Register X TCSRX: Timer X1 Bit : ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/W : R/ W Counter clear FRC clearing is disabled FRC clearing is enabled Timer overflow...
Page 987 H'D102: Free Running Counter H FRCH: Timer X1 H'D103: Free Running Counter L FRCL: Timer X1 Bit : Initial value : R/W : FRCH FRCL H'D104: Output Compare Register AH, BH OCRAH, OCRBH: Timer X1 H'D105: Output Compare Register AL, BL OCRAL, OCRBL: Timer X1 OCRA, OCRB Bit : Initial value :...
Page 988 H'D106: Timer Control Register X TCRX: Timer X1 Bit : IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value : R/W : Clock selct bit CKS1 CKS0 Clock select Internal clock: count at φ/4 Internal clock: count at φ/16 Internal clock: count at φ/64 DVCFG: Edge detection p ulse selected by CFG...
Page 989 H'D107: Timer Output Compare Control Register TOCR: Timer X1 Bit : ICSB ICSC ICSD OSRS OLVLA OLVLB Initial value : R/W : Output level B Low level High level Output level A Low level High level Output enable B Output compare B output is disabled Output compare B output is enabled Output enable A Output compare A output is disabled...
Page 990 H'D108: Input Capture Register AH ICRAH: Timer X1 H'D109: Input Capture Register AL ICRAL: Timer X1 H'D10A: Input Capture Register BH ICRBH: Timer X1 H'D10B: Input Capture Register BL ICRBL: Timer X1 H'D10C: Input Capture Register CH ICRCH: Timer X1 H'D10D: Input Capture Register CL ICRCL: Timer X1 H'D10E: Input Capture Register DH ICRDH: Timer X1 H'D10F: Input Capture Register DL ICRDL: Timer X1...
Page 991 H'D110: Timer Mode Register B TMB: Timer B Bit : TMB17 TMBIF TMBIE TMB12 TMB11 TMB10 — — Initial value : R/(W) * — — R/W : Clock select bit Clock select TMB12 TMB11 TMB10 Internal clock: Count at φ/16384 Internal clock: Count at φ/4096 Internal clock: Count at φ/1024 Internal clock: Count at φ/512...
Page 992 H'D111: Timer Load RegisterB TLB: TimerB Bit : TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10 Initial value : R/W : H'D112: Timer L Mode Register LMR: Timer L Bit : LMIF LMIE IMR3 IMR2 IMR1 IMR0 — — Initial value : R/(W) * —...
Page 993 H'D113: Linear Time Counter LTC: Timer L Bit : LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : R/W : H'D113: Reload/Compare Match Register RCR: Timer L Bit : RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 Initial value : R/W : Rev.
Page 994 H'D118: Timer R Mode Register 1 TMRM1: Timer R Bit : CLR2 AC/BR RLCK PS21 PS20 RLD/CAP Initial value : R/W : TMRU-1 capture signal select bit Capture signal at CFG rising edge Capture signal at IRQ3 edge TMRU-1 operation mode select bit TMRU-1 functions as reload timer TMRU-1 functions as capture timer TMRU-2 clock source select bits...
Page 995 H'D119: Timer R Mode Register TMRM2: Timer R Bit : PS11 PS10 PS31 PS30 CP/SLM CAPF Initial value : R/(W) * R/(W) * R/W : Slow tracking mono-multi flag [Clearing conditions] When 0 is written after reading 1 [Setting conditions] When slow tracking mono-multi ends while CP/SLM bit = 1 Capture signal flag...
Page 996 H'D11A: Timer R Capture Register 1 TMRCP1: Time R Bit : TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 Initial value : R/W : H'D11B: Timer R Capture Register 2 TMRCP2: Time R Bit : TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20...
Page 997 H'D11F: Timer R Control/Status Register TMRCS: Timer R Bit : TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 — — Initial value : R/(W) * R/(W) * R/(W) * — — R/W : TMRI1 interrupt request flag [Clearing conditions] When 0 is written after reading 1 [Setting conditions] When TMRU-1 underflows TMRI2 interrupt request flag...
Page 998 H'D120: PWM Data Register L PWDRL: 14-Bit PWM Bit : PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value : R/W : H'D121: PWM Data Register U PWDRU: 14-Bit PWM Bit : — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value : —...
Page 999 H'D128: 8-Bit PWM Data Register 2 PWR2: 8-Bit PWM Bit : PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20 Initial value : R/W : H'D129: 8-Bit PWM Data Register 3 PWR3: 8-Bit PWM Bit : PW37 PW36 PW35 PW34 PW33 PW32 PW31 PW30...
Page 1000 H'D12D: Prescaler Unit Control/Status Register PCSR: PSU Bit : — ICIF ICIE ICEG NCon/off DCS2 DCS1 DCS0 Initial value : R/(W) * R/W : — Frequency division clock output select bits Frequency division DCS2 DCS1 DCS0 clodk output select PSS, output φ/32 PSS, output φ/16 PSS, output φ/8 PSS, output φ/4...

This manual is also suitable for:

Hitachi h8s/2194 f-ztatHitachi h8s/2194c seriesHitachi h8s/2194c f-ztatHitachi h8s/2194Hitachi hd6432194 Hitachi hd64f2194 ... Show all

Renesas Hitachi H8S/2194 Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Power-Down State

Section 5 Exception Handling

Section 6 Interrupt Controller

Section 7 ROM (H8S/2194 Series)

Section 8 ROM (H8S/2194C Series)

Section 9 RAM

Section 10 Clock Pulse Generator

Section 11 I/O Port

Section 12 Timer a

Section 13 Timer B

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Summary of Contents for Renesas Hitachi H8S/2194 Series