Timing Of Timer Output At Compare-Match; Timing Of Counter Clear At Compare-Match; Figure 10.7 Timing Of Cmf Setting At Compare-Match; Figure 10.8 Timing Of Toggled Timer Output By Compare-Match A Signal - Renesas H8S/2111B Hardware Manual

φ
TCNT
TCOR
Compare-match
signal
CMF

Figure 10.7 Timing of CMF Setting at Compare-Match

10.5.3

Timing of Timer Output at Compare-Match

When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 10.8 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
φ
Compare-match A
signal
Timer output pin

Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal

10.5.4

Timing of Counter Clear at Compare-Match

TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 10.9 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
TCNT

Figure 10.9 Timing of Counter Clear by Compare-Match

Rev. 1.00, 05/04, page 208 of 544
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