Timing Of Counter Clear At Compare-Match; Tcnt External Reset Timing - Renesas H8S/2100 Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.5.4

Timing of Counter Clear at Compare-Match

TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
TCNT
Figure 13.8 Timing of Counter Clear by Compare-Match
13.5.5

TCNT External Reset Timing

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
13.9 shows the timing of clearing the counter by an external reset input.
φ
External reset
input pin
Clear signal
TCNT
Figure 13.9 Timing of Counter Clear by External Reset Input
Rev. 1.00 Apr. 28, 2008 Page 378 of 994
REJ09B0452-0100
N
N – 1
H'00
N H'00