Instruction Set; Table 2.1 Instruction Classification - Renesas H8S Series Hardware Manual

Section 2 CPU
2.6

Instruction Set

The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.
Table 2.1 Instruction Classification
Function Instructions
Data transfer MOV
POP *
LDM, STM
MOVFPE *
Arithmetic ADD, SUB, CMP, NEG
operations
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS *
MAC, LDMAC, STMAC, CLRMAC
Logic operations AND, OR, XOR, NOT
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Bcc *
Branch
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
Block data transfer EEPMOV
Legend: B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 6.00 Mar 15, 2006 page 30 of 570
REJ09B0211-0600
1 , PUSH * 1
3 , MOVTPE * 3
4
2
, JMP, BSR, JSR, RTS
Size Types
B/W/L 5
W/L
L
B
B/W/L 23
B
B/W/L
L
B/W
W/L
B
—
B/W/L 4
8
B 14
— 5
9
— 1
Total: 69