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2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.
Table 2.1
Instruction Classification
Function
Data transfer
Arithmetic
operation
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer EEPMOV
Notes: B-byte; W-word; L-longword.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and
MOV.L ERn,@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Instructions
MOV
1
1
POP*
, PUSH*
LDM, STM
3
MOVFPE*
, MOVTPE*
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
4
TAS*
MAC, LDMAC, STMAC, CLRMAC
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc*
, JMP, BSR, JSR, RTS
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
3
Rev. 1.00 Apr. 28, 2008 Page 45 of 994
Section 2 CPU
Size
Types
B/W/L 5
W/L
L
B
B/W/L 23
B
B/W/L
L
B/W
W/L
B
B/W/L 4
B
14
5
9
1
Total: 69
REJ09B0452-0100
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