Block Transfer Mode - Renesas F-ZTAT H8 Series Hardware Manual

Section 8 DMA Controller
8.4.6

Block Transfer Mode

In block transfer mode the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 8.10 indicates the register functions in block transfer mode.
Table 8.10 Register Functions in Block Transfer Mode
Register
23
MARA
23
MARB
7
ETCRAH
7
ETCRAL
15
ETCRB
Legend
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
Rev. 7.00 Sep 21, 2005 page 232 of 878
REJ09B0259-0700
Function
Source address
0
register
Destination
0
address register
Block size
0
counter
Initial block size
0
Block transfer
0
counter
Initial Setting Operation
Source address Incremented or
decremented once per
transfer, or held fixed
Destination Incremented or
address decremented once per
transfer, or held fixed
Block size Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRAL
Block size Held fixed
Number of block Decremented once per
transfers block transfer until H'0000
is reached and the
transfer ends