Block Transfer Mode; Block Transfer Example - Renesas NU85E Preliminary User's Manual

7.8.4 Block transfer mode

In block transfer mode, once transfer begins, the transfers continue without releasing the bus until a terminal count
occurs. No other DMA transfer requests are acknowledged during a block transfer.
After the block transfer ends and the DMAC has released the bus, another DMA transfer can be acknowledged.
Although it is prohibited to insert a CPU bus cycle during a block transfer, bus mastership can be transferred even
during a block transfer in response to a request by the external bus master (including SDRAM refresh).
Figure 7-22 shows a block transfer mode example. It is a block transfer mode example in which a higher priority
DMA transfer request is generated. DMA channels 2 and 3 are used for a block transfer.
DMARQ2
(Input)
DMARQ3
(Input)
CPU CPU CPU DMA3 DMA3
CHAPTER 7 DMAC
Figure 7-22. Block Transfer Example
DMA3 DMA3 DMA3 DMA3
Preliminary User's Manual A14874EJ3V0UM
DMA3 DMA3 CPU DMA2 DMA2 DMA2
The bus is always released
DMA channel 3 terminal count
DMA2 DMA2
171