Figure 7.21 Example Of Full Address Mode Transfer (Block Transfer Mode) - Renesas H8S/2368 Series Hardware Manual

DMA
read
Address bus
Bus release

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)

A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is
generated during data transfer, block transfer operation is not affected until data transfer for one
block has ended.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel DREQ DREQ DREQ
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
DMA DMA DMA
write read write
Block transfer
DMA DMA DMA
dead read write
Bus release Last block transfer
Rev. 2.00, 05/03, page 253 of 820
DMA DMA DMA
read write dead
Bus
release