Conflict Between Tcnt Write And Increment; Figure 13.14 Conflict Between Tcnt Write And Clear; Figure 13.15 Conflict Between Tcnt Write And Increment - Renesas H8S/2158 User Manual

Section 13 8-Bit Timer (TMR)
φ
Address
Internal write signal
Counter clear signal
TCNT

Figure 13.14 Conflict between TCNT Write and Clear

13.9.2

Conflict between TCNT Write and Increment

If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure
13.15, the write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 13.15 Conflict between TCNT Write and Increment

Rev. 3.00 Jan 25, 2006 page 340 of 872
REJ09B0286-0300
TCNT write cycle by CPU
T 1 T 2
TCNT address
N
TCNT write cycle by CPU
T 1 T 2
TCNT address
N
H'00
M
Counter write data