10.10.5 Contention Between Tcnt Write And Increment Operations; Figure 10.45 Contention Between Tcnt Write And Clear Operations; Figure 10.46 Contention Between Tcnt Write And Increment Operations - Renesas H8S/2368 Series Hardware Manual

φ
Address
Write signal
Counter clearing
signal
TCNT

Figure 10.45 Contention between TCNT Write and Clear Operations

10.10.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T
and TCNT is not incremented. Figure 10.46 shows the timing in this case.
φ
Address
Write signal
TCNT input
clock
TCNT

Figure 10.46 Contention between TCNT Write and Increment Operations

Rev. 2.00, 05/03, page 446 of 820
TCNT write cycle
T
1
TCNT address
N
state of a TCNT write cycle, the TCNT write takes precedence
2
TCNT write cycle
T
1
TCNT address
N
TCNT write data
T
2
H'0000
T
2
M