Interrupt Exception Handling Vector Tables - Renesas H8S/2100 Series Hardware Manual

6.5

Interrupt Exception Handling Vector Tables

Tables 6.5 and 6.6 list interrupt exception handling sources, vector addresses, and interrupt
priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for
the vector addresses by the EIVS bit in system control register 3 (SYSCR3).
For default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the interrupt control
level and the I and UI bits in CCR are given priority and processed before interrupt requests from
modules that are set to interrupt control level 0 (no priority).
Table 6.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities
(H8S/2140B Group Compatible Vector Mode)
Origin of
Interrupt
Source Name
External pin NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6, KIN7 to KIN0
IRQ7, KIN15 to KIN8
— Reserved for system use
WDT_0 WOVI0 (Interval timer)
WDT_1 WOVI1 (Interval timer)
— Address break
A/D converter ADI (A/D conversion end)
— Reserved for system use
External pin WUE7 to WUE0
WUE15 to WUE8
Vector Address
Vector
Number Advanced Mode
7 H'00001C
16 H'000040
17 H'000044
18 H'000048
19 H'00004C
20 H'000050
21 H'000054
22 H'000058
23 H'00005C
24 H'000060
25 H'000064
26 H'000068
27 H'00006C
28 H'000070
29 H'000074
 
31 H'00007C
32 H'000080
33 H'000084
Rev. 1.00 May 09, 2008 Page 123 of 954
Section 6 Interrupt Controller
ICR Priority
— High
ICRA7
ICRA6
ICRA5
ICRA4
ICRA3
—
ICRA1
ICRA0
—
ICRB7
—
ICRD4 Low
REJ09B0462-0100