Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1508

ADSP-SC58x USB Register Descriptions
Table 27-21: USB_EP0I_CSR[N]_H Register Fields (Continued)
Bit No.
(Access)
5 REQPKT
(R/W)
4 TOERR
(R/W0C)
3 SETUPPKT
(R/W1S)
2 RXSTALL
(R/W0C)
1 TXPKTRDY
(R/W1S)
27–96
Bit Name
Request Packet.
The USB_EP0I_CSR[N]_H.REQPKT bit directs (in host mode) the USB control-
ler to request an IN transaction. This bit is cleared when the
USB_EP0I_CSR[N]_H.RXPKTRDY bit is set.
Timeout Error.
The USB_EP0I_CSR[N]_H.TOERR bit indicates (in host mode) when three at-
tempts have been made to perform a transaction with no response from the peripheral.
The processor core should clear this bit. An interrupt is generated when this bit is set.
Setup Packet.
The USB_EP0I_CSR[N]_H.SETUPPKT bit directs (in host mode) the USB con-
troller to send a SETUP token instead of an OUT token for the transaction. This bit is
set at the same time as the USB_EP0I_CSR[N]_H.TXPKTRDY bit is set.
Rx Stall.
The USB_EP0I_CSR[N]_H.RXSTALL bit indicates (in host mode) when a
STALL handshake is received. The processor core should clear this bit.
Tx Packet Ready.
The USB_EP0I_CSR[N]_H.TXPKTRDY bit should be set (in host mode) by the
processor core after loading a data packet into the FIFO. This bit is cleared automati-
cally when the data packet is transmitted. An interrupt is generated (if enabled) when
the bit is cleared.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Request
1 Send IN Tokens to Device
0 No Status
1 Timeout Error
0 No Request
1 Send SETUP token
0 No Status
1 Stall Received from Device
0 No Tx Packet
1 Tx Packet in Endpoint FIFO