Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1491

Host High-Speed Return to Normal Register
The
USB_CT_HHSRTN
to the return to normal mode operation. This value is multiplied by 4 times the XCLK period (or 16.7 ns). The
default setting corresponds to a delay of 100us.
Figure 27-35: USB_CT_HHSRTN Register Diagram
Table 27-11: USB_CT_HHSRTN Register Fields
Bit No.
(Access)
14:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register selects the delay from the end of the high-speed resume signaling (acting as a host)
15 14 13
0 0 0
VALUE (R/W)
Host High-Speed Return to Normal
Value
Bit Name
Host High-Speed Return to Normal Value.
12 11 10 9 8 7 6 5
0 0 1 0 1 1 1 1
Description/Enumeration
ADSP-SC58x USB Register Descriptions
4 3 2 1 0
0 0 1 1 0
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