Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1509

Table 27-21: USB_EP0I_CSR[N]_H Register Fields (Continued)
Bit No.
(Access)
0 RXPKTRDY
(R/W0C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Rx Packet Ready.
The USB_EP0I_CSR[N]_H.RXPKTRDY is set (in host mode) when a data packet
is received. An interrupt is generated (if enabled) when this bit is set. The processor
core should clear this bit when the packet is read from the FIFO.
ADSP-SC58x USB Register Descriptions
Description/Enumeration
0 No Rx Packet
1 Rx Packet in Endpoint FIFO
27–97