Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1507

Table 27-21: USB_EP0I_CSR[N]_H Register Fields (Continued)
Bit No.
(Access)
9 DATGL
(R/W)
8 FLUSHFIFO
(R/W)
7 NAKTO
(R/W0C)
6 STATUSPKT
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Data Toggle.
The USB_EP0I_CSR[N]_H.DATGL bit indicates (in host mode) the current state
of the endpoint 0 data toggle. If D10 is high, this bit may be written with the required
setting of the data toggle. If D10 is low, any value written to this bit is ignored. This
bit is only used in host mode.
Flush Endpoint FIFO.
The USB_EP0I_CSR[N]_H.FLUSHFIFO bit directs (in host mode) the USB
controller to flush data from the endpoint 0 FIFO and clear the
USB_EP0I_CSR[N]_H.TXPKTRDY and USB_EP0I_CSR[N]_H.RXPKTRDY
bits. The USB_EP0I_CSR[N]_H.FLUSHFIFO bit should only be set if the
USB_EP0I_CSR[N]_H.TXPKTRDY and USB_EP0I_CSR[N]_H.RXPKTRDY
bits are set.
Note that setting this bit at other times may cause data corruption.
NAK Timeout.
The USB_EP0I_CSR[N]_H.NAKTO bit indicates (in host mode) when endpoint 0
is halted following the receipt of NAK responses for longer than the time set by the
USB_EP0_NAKLIMIT[n]
the endpoint to continue.
Status Packet.
The USB_EP0I_CSR[N]_H.STATUSPKT bit directs (in host mode) the USB
controller to perform a status stage transaction. This bit is set at the same time as the
USB_EP0I_CSR[N]_H.TXPKTRDY and USB_EP0I_CSR[N]_H.RXPKTRDY
bits. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is
used for the status stage transaction.
ADSP-SC58x USB Register Descriptions
Description/Enumeration
0 DATA0 is Set
1 DATA1 is Set
0 No Flush
1 Flush Endpoint FIFO
register. The processor core should clear this bit to allow
0 No Status
1 Endpoint Halted (NAK Timeout)
0 No Request
1 Request Status Transaction
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