Overview; Features Of This Lsi - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Renesas microprocessor
1.

Overview

1.1

Features of This LSI

This LSI is a single-chip microcontroller that includes an Arm Cortex
peripheral functions required to configure a system.
This LSI includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache. This LSI also
includes on-chip peripheral functions necessary for system configuration, such as a 3-Mbyte (RZ/A1L and RZ/A1LU) or
2-Mbyte (RZ/A1LC) large-capacity RAM (128 Kbytes are shared by the data-retention RAM), data-retention RAM,
multi-function timer pulse unit 2, OS timer, realtime clock, serial communication interface with FIFO, serial
communication interface, I
interface, IEBus™* controller (RZ/A1L only), Renesas SPDIF interface, Renesas serial peripheral interface, SPI multi
I/O bus controller, CD-ROM decoder (RZ/A1L only), A/D converter, LIN interface (RZ/A1L only), Ethernet controller,
EthernetAVB (RZ/A1LU only), USB 2.0 host/function, video display controller 5, JPEG codec unit (RZ/A1LU only),
capture engine unit, SD host interface, MMC host interface, interrupt controller modules, and general I/O ports.
The features of this LSI are listed in Table 1.1.
Note: * IEBus (Inter Equipment Bus) is a trademark of Renesas Electronics Corporation.
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Jan 29, 2021
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C bus interface, serial sound interface, media local bus (RZ/A1L only), SCUX, CAN
®
-A9 processor along with the integrated
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Rev.6.00
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