ST STM32L4+ Series Reference Manual page 1210

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Advanced-control timers (TIM1/TIM8)

Timerclock = CK_CNT

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

Figure 299. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Timerclock = CK_CNT

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

Figure 298. Counter timing diagram, internal clock divided by 2

RM0432 Rev 6

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