ST STM32L4+ Series Reference Manual page 1214

Advanced-control timers (TIM1/TIM8)
37.3.4 External trigger input
The timer features an external trigger input ETR. It can be used as:
•
external clock (external clock mode 2, see
•
trigger for the slave mode (see
•
PWM reset input for cycle-by-cycle current regulation (see
Figure 304
ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed
by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.
ETR input
The ETR input comes from multiple sources: input pins (default configuration), comparator
outputs and analog watchdogs. The selection is done with:
• the ETRSEL[2:0] bitfield in the TIMx_OR2 register
•
the ETR_ADC1_RMP bitfield in the TIMxOR1[1:0] register
ETR inputs from
AF controller
ADC1_AWD1
ADC1_AWD2
ADC1_AWD3
ETR inputs from
AF controller
ADC2_AWD1
ADC2_AWD2
ADC2_AWD3
1214/2301
below describes the ETR input conditioning. The input polarity is defined with the
Figure 304. External trigger input block
ETR
0
Divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR
Figure 305. TIM1 ETR input circuitry
TIM1_OR1[1:0]
NC
Figure 306. TIM8 ETR input circuitry
TIM8_OR1[1:0]
NC
RM0432 Rev 6
Section 37.3.5)
Section 37.3.26)
ETRP
Filter
downcounter
f
DTS
ETF[3:0]
TIMx_SMCR
TIM1_OR2[16:14]
ETR legacy mode
COMP1
COMP2
NC
NC
NC
NC
NC
TIM8_OR2[16:14]
ETR legacy mode
NC
COMP2
NC
NC
NC
NC
NC
RM0432
Section 37.3.7)
To the Output mode controller
To the CK_PSC circuitry
To the Slave mode controller
MS34403V2
ETR input
MSv37631V1
ETR input
MSv64420V1