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Section 13 Serial Communication Interface
13.2.6
Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit
7
TIE
Initial value
0
Read/Write
R/W
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Rev. 4.00 Jan 26, 2006 page 488 of 938
REJ09B0276-0400
6
5
RIE
TE
0
0
R/W
R/W
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
4
3
2
RE
MPIE
TEIE
0
0
0
R/W
R/W
R/W
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock enable 1/0
hese bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
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