Serial Control Register (Scr) - Renesas F-ZTAT H8 Series Hardware Manual

Section 13 Serial Communication Interface
13.2.6

Serial Control Register (SCR)

SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit 7
TIE
Initial value 0
Read/Write R/W
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Rev. 7.00 Sep 21, 2005 page 460 of 878
REJ09B0259-0700
6 5
RIE TE RE
0 0
R/W R/W R/W
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
4 3 2
MPIE TEIE
0 0 0
R/W R/W
Transmit-end interrupt enable
Enables or disables transmit-
end interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
1 0
CKE1 CKE0
0 0
R/W R/W
Clock enable 1/0
These bits select the
SCI clock source