Serial Control Register (Scr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.6

Serial Control Register (SCR)

Note: • Some bits in SCR have different functions in serial communications interface mode and smart card interface
mode.
(1) Serial Communications Interface Mode (SMIF in SCMR = 0)
b7 b6
TIE RIE
Value after reset: 0 0
Bit Symbol Bit Name
b1, b0 CKE[1:0] Clock Enable
b2 TEIE Transmit End Interrupt Enable
b3 MPIE Multi-Processor Interrupt Enable
b4 RE Receive Enable
b5 TE Transmit Enable
b6 RIE Receive Interrupt Enable
b7 TIE Transmit Interrupt Enable
x: Don't care
Note 1. Writable only when TE = 0 and RE = 0.
Note 2. A 1 can be written only when TE = 0 and RE = 0, while the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written in
TE and RE. While the SMR.CM bit is 0, writing is enabled under any condition.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
TE RE MPIE TEIE
0 0 0 0
Description
(Asynchronous mode)
(Clock synchronous mode)
0: A TEI interrupt request is disabled
1: A TEI interrupt request is enabled
(Valid in asynchronous mode when SMR.MP = 1)
0: Normal reception
1: When the data with the multi-processor bit set to 0 is received,
0: Serial reception is disabled
1: Serial reception is enabled
0: Serial transmission is disabled
1: Serial transmission is enabled
0: RXI and ERI interrupt requests are disabled
1: RXI and ERI interrupt requests are enabled
0: A TXI interrupt request is disabled
1: A TXI interrupt request is enabled
b1 b0
CKE[1:0]
0 0
b1 b0
0 0: On-chip baud rate generator
The SCKn pin functions as general-purpose I/O port.
0 1: On-chip baud rate generator
The clock with the same frequency as the bit rate is output
from the SCKn pin.
1 x: External clock
SEMR.ABCS bit is 0:
The clock with a frequency 16 times the bit rate should be
input from the SCKn pin.
SEMR.ABCS bit is 1:
The clock with a frequency eight times the bit rate should
be input from the SCKn pin.
b1 b0
0 x: Internal clock
The SCKn pin functions as the clock output pin.
1 x: External clock
The SCKn pin functions as the clock input pin.
the data is not read, and setting the status flags ORER and
FER in SSR to 1 is disabled. When the data with the multi-
processor bit set to 1 is received, the MPIE bit is automatically
cleared to 0, and normal reception is resumed.
15. Serial Communications Interface
R/W
1
R/W*
R/W
R/W
2
R/W*
2
R/W*
R/W
R/W
15-8