Serial Control Register (Scr) - Renesas H8S Series Hardware Manual

14.3.6

Serial Control Register (SCR)

SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also
used to selection of the transfer clock source. For details on interrupt requests, refer to section
14.8, Interrupts. Some bit functions of SCR differ between normal serial communication interface
mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial Value
7 TIE 0
6 RIE 0
5 TE 0
4 RE 0
3 MPIE 0
2 TEIE 0
Section 14 Serial Communication Interface (SCI)
R/W Description
R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
R/W Receive Enable
When this bit is set to 1, reception is enabled.
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 14.5, Multiprocessor Communication
Function.
R/W Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled.
Rev. 6.00 Mar 15, 2006 page 321 of 570
REJ09B0211-0600