Ddr3B - Altera Cyclone V Reference Manual

Chapter 2: Board Components
Memory
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 6)
Board Reference
DDR3 x16 (U30)
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
K3
K9
J7
K7
L2
E7
D3
E3
F7
F2
August 2017 Altera Corporation
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DDR3B

The DDR3B SDRAM comprises of four ×16 devices with a single address and
command bus. This interface connects to the horizontal I/O banks on the right edge
of the FPGA and utilizes the soft memory controller.
This memory interface runs at a target frequency of 300 MHz for a maximum
theoretical bandwidth of over 38.40 Gbps.
Table 2–28 lists the DDR3B pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GT in terms of I/O setting and
direction.
Schematic Cyclone V GT
Signal Name Pin Number
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
AE34
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
AF32
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
AE30
DDR3B_DM0
AE32
DDR3B_DM1
AF31
DDR3B_DQ0
AD30
DDR3B_DQ1
AJ32
DDR3B_DQ2
I/O Standard
H29 1.5-V SSTL Class I
K28 1.5-V SSTL Class I
K34 1.5-V SSTL Class I
L32 1.5-V SSTL Class I
R32 1.5-V SSTL Class I
R33 1.5-V SSTL Class I
N32 1.5-V SSTL Class I
G33 1.5-V SSTL Class I
1.5-V SSTL Class I
L27 1.5-V SSTL Class I
V33 1.5-V SSTL Class I
U33 1.5-V SSTL Class I
T31 1.5-V SSTL Class I
T30 1.5-V SSTL Class I
J31 1.5-V SSTL Class I
N29 1.5-V SSTL Class I
P27 1.5-V SSTL Class I
N27 1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
R30
Class I
Differential 1.5-V SSTL
R29
Class I
V27 1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
2–43
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Cyclone V GT FPGA Development Board
Reference Manual