Specifying The Parameters For The Cyclone V Hard Ip For Pci Express - Altera Cyclone V User Manual

2–10
The following sections provide step-by-step instructions to create the example design
in Qsys. If you prefer, you can copy the completed system from the Quartus II
software installation, and then go to
on page
<install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/cv.

Specifying the Parameters for the Cyclone V Hard IP for PCI Express

This section guides you through the process of specifying parameters for the Cyclone
V Hard IP for PCI Express to create a Gen1 ×4 Endpoint.
1. Specify the System Settings parameters listed in
Table 2–9. System Settings Parameters
Number of Lanes
Lane Rate
Port type
Application interface
RX buffer credit allocation - performance for
received requests
Reference clock frequency
Use 62.5 MHz Application Layer clock for ×1
Use deprecated RX Avalon-ST data byte enable
port (rx_st_be)
Number of functions
1
Each function shares the parameter settings on the Device, Error Reporting, Link,
Slot, and Power Management tabs. Each function has separate parameter settings for
the Base Address Registers, Base and Limit Registers for Root Ports, Device
Identification Registers, and the PCI Express/PCI Capabilites parameters. When
you click on a Func<n> tab under the Port Functions heading, the tabs automatically
reflect the Func<n> tab selected.
2. Specify the Device parameters listed in
Table 2–10. Device
Maximum payload size
Number of tags supported
Completion timeout range
Implement completion timeout disable
3. On the Error Reporting tab, leave all options off.
Cyclone V Hard IP for PCI Express
2–16. The completed Qsys systems are located in the following directory:
Parameter
Parameter
"Generating the Simulation Model Using Qsys"
Table 2–9.
×4
Gen 1 (2.5 Gbps)
Native endpoint
Avalon-ST 64-bit
Low
100 MHz
Leave this option Off
Leave this option On.
1
Table 2–10.
256 bytes
November 2011 Altera Corporation
Chapter 2: Getting Started
Qsys Design Flow
Value
Value
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