Using The Epcq Flash Memory - Altera Cyclone V Reference Manual

2–14
Figure 2–4. PFL Configuration
2.5 V
2.5 V
56.2 Ω
2.5 V
56.2 Ω
Cyclone V GT FPGA Development Board
Reference Manual
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Figure 2–4 shows the PFL configuration.
100 Ω
MAX V CPLD
5M2210 System Controller
MAX_ERROR
MAX_LOAD
MAX_CONF_DONE
CLK_SEL
CLK_ENABLE
FPGA_nSTATUS
FACTORY_USER
ASSP_MODE
FPGA_nCONFIG
FPGA_CONF_DONE
CPU_RESETn
MAX_RESETn
FPGA_DATA [15:0]
FPGA_DCLK
PGM_CONFIG
PGM_SEL
FLASH_A [26:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
PGM_LED0
FLASH_RYBSYn
PGM_LED1
FLASH_CLK
PGM_LED2
FLASH_RSTn
FLASH_ADVn
CFI Flash
FLASH_A [26:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RYBSYn
FLASH_CLK
FLASH_RESETn
FLASH_WPn
FLASH_ADVn
f
For more information on the following topics, refer to the respective documents:
■ Board Update Portal, PFL design, and flash memory map storage, refer to the
Cyclone V GT FPGA Development Kit User
■ PFL megafunction, refer to

Using the EPCQ Flash Memory

To enable FPGA configuration using the EPCQ device, you must reconfigure the MAX
V device with a specific hardware design, which you can download.
For further information, refer to
on page 2–11.
2.5 V
50 MHz
100 MHz
1.8 V
10 kΩ
DNI 10 kΩ
Guide.
Parallel Flash Loader Megafunction User Guide.
"Configuring the MAX V Device to Program EPCQ"
Chapter 2: Board Components
FPGA Configuration
MSEL[4:0] also
Cyclone V FPGA
connects to the
MAX V CPLD
MSEL1
MSEL2
MSEL4
nSTATUS
nCONFIG
CONF_DONE
1 kΩ
nCE
MSEL0
1 kΩ
PS Port MSEL3
DATA [15:0]
Flash Interface
DCLK
August 2017 Altera Corporation